2 -- Functions to generate VHDL from FlatFunctions
7 import qualified Data.Foldable as Foldable
8 import qualified Data.List as List
9 import qualified Data.Map as Map
10 import qualified Maybe
11 import qualified Control.Monad as Monad
12 import qualified Control.Arrow as Arrow
13 import qualified Control.Monad.Trans.State as State
14 import qualified Data.Traversable as Traversable
15 import qualified Data.Monoid as Monoid
17 import qualified Data.Accessor.MonadState as MonadState
18 import Text.Regex.Posix
22 import qualified ForSyDe.Backend.VHDL.AST as AST
28 import qualified OccName
31 import qualified IdInfo
32 import qualified TyCon
33 import qualified TcType
34 import qualified DataCon
35 import qualified CoreSubst
36 import qualified CoreUtils
37 import Outputable ( showSDoc, ppr )
43 import TranslatorTypes
49 import GlobalNameTable
52 [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)]
53 -> [(AST.VHDLId, AST.DesignFile)]
55 createDesignFiles binds =
56 (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body]) :
57 map (Arrow.second $ AST.DesignFile full_context) units
60 init_session = VHDLSession Map.empty Map.empty Map.empty Map.empty globalNameTable
61 (units, final_session) =
62 State.runState (createLibraryUnits binds) init_session
63 tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
64 ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
65 vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
66 tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
67 tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) highId Nothing)
68 tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
70 AST.Library $ mkVHDLBasicId "IEEE",
71 mkUseAll ["IEEE", "std_logic_1164"],
72 mkUseAll ["IEEE", "numeric_std"]
75 mkUseAll ["work", "types"]
77 type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
78 type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
79 subProgSpecs = concat (map subProgSpec tyfun_decls)
80 subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec)
81 mktydecl :: (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn) -> AST.PackageDecItem
82 mktydecl (ty_id, Left ty_def) = AST.PDITD $ AST.TypeDec ty_id ty_def
83 mktydecl (ty_id, Right ty_def) = AST.PDISD $ AST.SubtypeDec ty_id ty_def
85 -- Create a use foo.bar.all statement. Takes a list of components in the used
86 -- name. Must contain at least two components
87 mkUseAll :: [String] -> AST.ContextItem
89 AST.Use $ from AST.:.: AST.All
91 base_prefix = (AST.NSimple $ mkVHDLBasicId $ head ss)
92 from = foldl select base_prefix (tail ss)
93 select prefix s = AST.NSelected $ prefix AST.:.: (AST.SSimple $ mkVHDLBasicId s)
96 [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)]
97 -> VHDLState [(AST.VHDLId, [AST.LibraryUnit])]
99 createLibraryUnits binds = do
100 entities <- Monad.mapM createEntity binds
101 archs <- Monad.mapM createArchitecture binds
104 let AST.EntityDec id _ = ent in
105 (id, [AST.LUEntity ent, AST.LUArch arch])
109 -- | Create an entity for a given function
111 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- | The function
112 -> VHDLState AST.EntityDec -- | The resulting entity
114 createEntity (fname, expr) = do
115 -- Strip off lambda's, these will be arguments
116 let (args, letexpr) = CoreSyn.collectBinders expr
117 args' <- Monad.mapM mkMap args
118 -- There must be a let at top level
119 let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr
121 let vhdl_id = mkVHDLBasicId $ bndrToString fname ++ "_" ++ varToStringUniq fname
122 let ent_decl' = createEntityAST vhdl_id args' res'
123 let AST.EntityDec entity_id _ = ent_decl'
124 let signature = Entity entity_id args' res'
125 modA vsSignatures (Map.insert fname signature)
129 --[(SignalId, SignalInfo)]
131 -> VHDLState VHDLSignalMapElement
132 -- We only need the vsTypes element from the state
135 --info = Maybe.fromMaybe
136 -- (error $ "Signal not found in the name map? This should not happen!")
137 -- (lookup id sigmap)
138 -- Assume the bndr has a valid VHDL id already
139 id = bndrToVHDLId bndr
140 ty = Var.varType bndr
142 if True -- isPortSigUse $ sigUse info
144 type_mark <- vhdl_ty ty
145 return $ Just (id, type_mark)
150 -- | Create the VHDL AST for an entity
152 AST.VHDLId -- | The name of the function
153 -> [VHDLSignalMapElement] -- | The entity's arguments
154 -> VHDLSignalMapElement -- | The entity's result
155 -> AST.EntityDec -- | The entity with the ent_decl filled in as well
157 createEntityAST vhdl_id args res =
158 AST.EntityDec vhdl_id ports
160 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
161 ports = Maybe.catMaybes $
162 map (mkIfaceSigDec AST.In) args
163 ++ [mkIfaceSigDec AST.Out res]
165 -- Add a clk port if we have state
166 clk_port = if True -- hasState hsfunc
168 Just $ AST.IfaceSigDec (mkVHDLExtId "clk") AST.In VHDL.std_logic_ty
172 -- | Create a port declaration
174 AST.Mode -- | The mode for the port (In / Out)
175 -> Maybe (AST.VHDLId, AST.TypeMark) -- | The id and type for the port
176 -> Maybe AST.IfaceSigDec -- | The resulting port declaration
178 mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
179 mkIfaceSigDec _ Nothing = Nothing
181 -- | Generate a VHDL entity name for the given hsfunc
183 -- TODO: This doesn't work for functions with multiple signatures!
184 -- Use a Basic Id, since using extended id's for entities throws off
185 -- precision and causes problems when generating filenames.
186 mkVHDLBasicId $ hsFuncName hsfunc
188 -- | Create an architecture for a given function
189 createArchitecture ::
190 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The function
191 -> VHDLState AST.ArchBody -- ^ The architecture for this function
193 createArchitecture (fname, expr) = do
194 signaturemap <- getA vsSignatures
195 let signature = Maybe.fromMaybe
196 (error $ "Generating architecture for function " ++ (pprString fname) ++ "without signature? This should not happen!")
197 (Map.lookup fname signaturemap)
198 let entity_id = ent_id signature
199 -- Strip off lambda's, these will be arguments
200 let (args, letexpr) = CoreSyn.collectBinders expr
201 -- There must be a let at top level
202 let (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) = letexpr
204 -- Create signal declarations for all binders in the let expression, except
205 -- for the output port (that will already have an output port declared in
207 sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
208 let sig_decs = Maybe.catMaybes $ sig_dec_maybes
210 statementss <- Monad.mapM mkConcSm binds
211 let statements = concat statementss
212 return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
214 procs = map mkStateProcSm [] -- (makeStatePairs flatfunc)
215 procs' = map AST.CSPSm procs
216 -- mkSigDec only uses vsTypes from the state
219 -- | Looks up all pairs of old state, new state signals, together with
220 -- the state id they represent.
221 makeStatePairs :: FlatFunction -> [(StateId, SignalInfo, SignalInfo)]
222 makeStatePairs flatfunc =
223 [(Maybe.fromJust $ oldStateId $ sigUse old_info, old_info, new_info)
224 | old_info <- map snd (flat_sigs flatfunc)
225 , new_info <- map snd (flat_sigs flatfunc)
226 -- old_info must be an old state (and, because of the next equality,
227 -- new_info must be a new state).
228 , Maybe.isJust $ oldStateId $ sigUse old_info
229 -- And the state numbers must match
230 , (oldStateId $ sigUse old_info) == (newStateId $ sigUse new_info)]
232 -- Replace the second tuple element with the corresponding SignalInfo
233 --args_states = map (Arrow.second $ signalInfo sigs) args
234 mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm
235 mkStateProcSm (num, old, new) =
236 AST.ProcSm label [clk] [statement]
238 label = mkVHDLExtId $ "state_" ++ (show num)
239 clk = mkVHDLExtId "clk"
240 rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
241 wform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple $ getSignalId new) Nothing]
242 assign = AST.SigAssign (AST.NSimple $ getSignalId old) wform
243 rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
244 statement = AST.IfSm rising_edge_clk [assign] [] Nothing
246 mkSigDec :: CoreSyn.CoreBndr -> VHDLState (Maybe AST.SigDec)
248 if True then do --isInternalSigUse use || isStateSigUse use then do
249 type_mark <- vhdl_ty $ Var.varType bndr
250 return $ Just (AST.SigDec (bndrToVHDLId bndr) type_mark Nothing)
254 -- | Creates a VHDL Id from a named SignalInfo. Errors out if the SignalInfo
256 getSignalId :: SignalInfo -> AST.VHDLId
258 mkVHDLExtId $ Maybe.fromMaybe
259 (error $ "Unnamed signal? This should not happen!")
262 -- | Transforms a core binding into a VHDL concurrent statement
264 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
265 -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
268 -- Ignore Cast expressions, they should not longer have any meaning as long as
269 -- the type works out.
270 mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr)
272 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
273 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
274 let valargs' = filter isValArg args
275 let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs'
276 case Var.globalIdVarDetails f of
277 IdInfo.DataConWorkId dc ->
278 -- It's a datacon. Create a record from its arguments.
279 -- First, filter out type args. TODO: Is this the best way to do this?
280 -- The types should already have been taken into acocunt when creating
281 -- the signal, so this should probably work...
282 --let valargs = filter isValArg args in
283 if all is_var valargs then do
284 labels <- getFieldLabels (CoreUtils.exprType app)
285 return $ zipWith mkassign labels valargs
287 error $ "VHDL.mkConcSm Not in normal form: One ore more complex arguments: " ++ pprString args
289 mkassign :: AST.VHDLId -> CoreExpr -> AST.ConcSm
290 mkassign label (Var arg) =
291 let sel_name = mkSelectedName bndr label in
292 mkUncondAssign (Right sel_name) (varToVHDLExpr arg)
293 IdInfo.VanillaGlobal -> do
294 -- It's a global value imported from elsewhere. These can be builtin
296 funSignatures <- getA vsNameTable
297 signatures <- getA vsSignatures
298 case (Map.lookup (bndrToString f) funSignatures) of
299 Just (arg_count, builder) ->
300 if length valargs == arg_count then
304 sigs = map (varToVHDLExpr.varBndr) valargs
305 func = funBuilder sigs
306 src_wform = AST.Wform [AST.WformElem func Nothing]
307 dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
308 assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
310 return [AST.CSSASm assign]
313 ty = Var.varType bndr
315 sigs = map varBndr valargs
316 signature = Maybe.fromMaybe
317 (error $ "Using function '" ++ (bndrToString (head sigs)) ++ "' without signature? This should not happen!")
318 (Map.lookup (head sigs) signatures)
319 arg_names = map (mkVHDLExtId . bndrToString) (tail sigs)
320 dst_name = mkVHDLExtId (bndrToString bndr)
321 genSm = genBuilder len signature (arg_names ++ [dst_name])
322 in return [AST.CSGSm genSm]
324 error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs
325 Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
326 IdInfo.NotGlobalId -> do
327 signatures <- getA vsSignatures
328 -- This is a local id, so it should be a function whose definition we
329 -- have and which can be turned into a component instantiation.
331 signature = Maybe.fromMaybe
332 (error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!")
333 (Map.lookup f signatures)
334 entity_id = ent_id signature
335 label = "comp_ins_" ++ bndrToString bndr
336 -- Add a clk port if we have state
337 --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
338 clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
339 --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
340 portmaps = clk_port : mkAssocElems args bndr signature
342 return [AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)]
343 details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
345 -- A single alt case must be a selector. This means thee scrutinee is a simple
346 -- variable, the alternative is a dataalt with a single non-wild binder that
348 mkConcSm (bndr, expr@(Case (Var scrut) b ty [alt])) =
350 (DataAlt dc, bndrs, (Var sel_bndr)) -> do
351 case List.elemIndex sel_bndr bndrs of
353 labels <- getFieldLabels (Id.idType scrut)
354 let label = labels!!i
355 let sel_name = mkSelectedName scrut label
356 let sel_expr = AST.PrimName sel_name
357 return [mkUncondAssign (Left bndr) sel_expr]
358 Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
360 _ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
362 -- Multiple case alt are be conditional assignments and have only wild
363 -- binders in the alts and only variables in the case values and a variable
364 -- for a scrutinee. We check the constructor of the second alt, since the
365 -- first is the default case, if there is any.
366 mkConcSm (bndr, (Case (Var scrut) b ty [(_, _, Var false), (con, _, Var true)])) =
368 cond_expr = (varToVHDLExpr scrut) AST.:=: (altconToVHDLExpr con)
369 true_expr = (varToVHDLExpr true)
370 false_expr = (varToVHDLExpr false)
372 return [mkCondAssign (Left bndr) cond_expr true_expr false_expr]
373 mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
374 mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
375 mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
377 -- Create an unconditional assignment statement
379 Either CoreBndr AST.VHDLName -- ^ The signal to assign to
380 -> AST.Expr -- ^ The expression to assign
381 -> AST.ConcSm -- ^ The resulting concurrent statement
382 mkUncondAssign dst expr = mkAssign dst Nothing expr
384 -- Create a conditional assignment statement
386 Either CoreBndr AST.VHDLName -- ^ The signal to assign to
387 -> AST.Expr -- ^ The condition
388 -> AST.Expr -- ^ The value when true
389 -> AST.Expr -- ^ The value when false
390 -> AST.ConcSm -- ^ The resulting concurrent statement
391 mkCondAssign dst cond true false = mkAssign dst (Just (cond, true)) false
393 -- Create a conditional or unconditional assignment statement
395 Either CoreBndr AST.VHDLName -> -- ^ The signal to assign to
396 Maybe (AST.Expr , AST.Expr) -> -- ^ Optionally, the condition to test for
397 -- and the value to assign when true.
398 AST.Expr -> -- ^ The value to assign when false or no condition
399 AST.ConcSm -- ^ The resulting concurrent statement
401 mkAssign dst cond false_expr =
403 -- I'm not 100% how this assignment AST works, but this gets us what we
405 whenelse = case cond of
406 Just (cond_expr, true_expr) ->
408 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
410 [AST.WhenElse true_wform cond_expr]
412 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
413 dst_name = case dst of
414 Left bndr -> AST.NSimple (bndrToVHDLId bndr)
416 assign = dst_name AST.:<==: (AST.ConWforms whenelse false_wform Nothing)
420 -- Create a record field selector that selects the given label from the record
421 -- stored in the given binder.
422 mkSelectedName :: CoreBndr -> AST.VHDLId -> AST.VHDLName
423 mkSelectedName bndr label =
425 sel_prefix = AST.NSimple $ bndrToVHDLId bndr
426 sel_suffix = AST.SSimple $ label
428 AST.NSelected $ sel_prefix AST.:.: sel_suffix
430 -- Finds the field labels for VHDL type generated for the given Core type,
431 -- which must result in a record type.
432 getFieldLabels :: Type.Type -> VHDLState [AST.VHDLId]
433 getFieldLabels ty = do
434 -- Ensure that the type is generated (but throw away it's VHDLId)
436 -- Get the types map, lookup and unpack the VHDL TypeDef
437 types <- getA vsTypes
438 case Map.lookup (OrdType ty) types of
439 Just (_, Left (AST.TDR (AST.RecordTypeDef elems))) -> return $ map (\(AST.ElementDec id _) -> id) elems
440 _ -> error $ "VHDL.getFieldLabels Type not found or not a record type? This should not happen! Type: " ++ (show ty)
442 -- Turn a variable reference into a AST expression
443 varToVHDLExpr :: Var.Var -> AST.Expr
445 case Id.isDataConWorkId_maybe var of
446 Just dc -> dataconToVHDLExpr dc
447 -- This is a dataconstructor.
448 -- Not a datacon, just another signal. Perhaps we should check for
449 -- local/global here as well?
450 Nothing -> AST.PrimName $ AST.NSimple $ bndrToVHDLId var
452 -- Turn a alternative constructor into an AST expression. For
453 -- dataconstructors, this is only the constructor itself, not any arguments it
454 -- has. Should not be called with a DEFAULT constructor.
455 altconToVHDLExpr :: CoreSyn.AltCon -> AST.Expr
456 altconToVHDLExpr (DataAlt dc) = dataconToVHDLExpr dc
458 altconToVHDLExpr (LitAlt _) = error "VHDL.conToVHDLExpr Literals not support in case alternatives yet"
459 altconToVHDLExpr DEFAULT = error "VHDL.conToVHDLExpr DEFAULT alternative should not occur here!"
461 -- Turn a datacon (without arguments!) into a VHDL expression.
462 dataconToVHDLExpr :: DataCon.DataCon -> AST.Expr
463 dataconToVHDLExpr dc = AST.PrimLit lit
465 tycon = DataCon.dataConTyCon dc
466 tyname = TyCon.tyConName tycon
467 dcname = DataCon.dataConName dc
468 lit = case Name.getOccString tyname of
469 -- TODO: Do something more robust than string matching
470 "Bit" -> case Name.getOccString dcname of "High" -> "'1'"; "Low" -> "'0'"
471 "Bool" -> case Name.getOccString dcname of "True" -> "true"; "False" -> "false"
475 mkConcSm sigs (UncondDef src dst) _ = do
476 src_expr <- vhdl_expr src
477 let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
478 let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
479 let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
480 return $ AST.CSSASm assign
482 vhdl_expr (Left id) = return $ mkIdExpr sigs id
483 vhdl_expr (Right expr) =
486 return $ (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
487 (Literal lit Nothing) ->
488 return $ AST.PrimLit lit
489 (Literal lit (Just ty)) -> do
490 -- Create a cast expression, which is just a function call using the
491 -- type name as the function name.
492 let litexpr = AST.PrimLit lit
494 let ty_name = AST.NSimple ty_id
495 let args = [Nothing AST.:=>: (AST.ADExpr litexpr)]
496 return $ AST.PrimFCall $ AST.FCall ty_name args
498 return $ (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
500 mkConcSm sigs (CondDef cond true false dst) _ =
502 cond_expr = mkIdExpr sigs cond
503 true_expr = mkIdExpr sigs true
504 false_expr = mkIdExpr sigs false
505 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
506 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
507 whenelse = AST.WhenElse true_wform cond_expr
508 dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
509 assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
511 return $ AST.CSSASm assign
513 -- | Turn a SignalId into a VHDL Expr
514 mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr
516 let src_name = AST.NSimple (getSignalId $ signalInfo sigs id) in
517 AST.PrimName src_name
520 [CoreSyn.CoreExpr] -- | The argument that are applied to function
521 -> CoreSyn.CoreBndr -- | The binder in which to store the result
522 -> Entity -- | The entity to map against.
523 -> [AST.AssocElem] -- | The resulting port maps
525 mkAssocElems args res entity =
526 -- Create the actual AssocElems
527 Maybe.catMaybes $ zipWith mkAssocElem ports sigs
529 -- Turn the ports and signals from a map into a flat list. This works,
530 -- since the maps must have an identical form by definition. TODO: Check
532 arg_ports = ent_args entity
533 res_port = ent_res entity
534 -- Extract the id part from the (id, type) tuple
535 ports = map (Monad.liftM fst) (res_port : arg_ports)
536 -- Translate signal numbers into names
537 sigs = (bndrToString res : map (bndrToString.varBndr) args)
539 -- Turns a Var CoreExpr into the Id inside it. Will of course only work for
540 -- simple Var CoreExprs, not complexer ones.
541 varBndr :: CoreSyn.CoreExpr -> Var.Id
542 varBndr (CoreSyn.Var id) = id
544 -- | Look up a signal in the signal name map
545 lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
546 lookupSigName sigs sig = name
548 info = Maybe.fromMaybe
549 (error $ "Unknown signal " ++ (show sig) ++ " used? This should not happen!")
551 name = Maybe.fromMaybe
552 (error $ "Unnamed signal " ++ (show sig) ++ " used? This should not happen!")
555 -- | Create an VHDL port -> signal association
556 mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
557 mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLExtId signal)))
558 mkAssocElem Nothing _ = Nothing
560 -- | The VHDL Bit type
561 bit_ty :: AST.TypeMark
562 bit_ty = AST.unsafeVHDLBasicId "Bit"
564 -- | The VHDL Boolean type
565 bool_ty :: AST.TypeMark
566 bool_ty = AST.unsafeVHDLBasicId "Boolean"
568 -- | The VHDL std_logic
569 std_logic_ty :: AST.TypeMark
570 std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
572 -- Translate a Haskell type to a VHDL type
573 vhdl_ty :: Type.Type -> VHDLState AST.TypeMark
575 typemap <- getA vsTypes
576 let builtin_ty = do -- See if this is a tycon and lookup its name
577 (tycon, args) <- Type.splitTyConApp_maybe ty
578 let name = Name.getOccString (TyCon.tyConName tycon)
579 Map.lookup name builtin_types
580 -- If not a builtin type, try the custom types
581 let existing_ty = (fmap fst) $ Map.lookup (OrdType ty) typemap
582 case Monoid.getFirst $ Monoid.mconcat (map Monoid.First [builtin_ty, existing_ty]) of
583 -- Found a type, return it
585 -- No type yet, try to construct it
587 newty_maybe <- (construct_vhdl_ty ty)
589 Just (ty_id, ty_def) -> do
590 -- TODO: Check name uniqueness
591 modA vsTypes (Map.insert (OrdType ty) (ty_id, ty_def))
593 Nothing -> error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty)
595 -- Construct a new VHDL type for the given Haskell type.
596 construct_vhdl_ty :: Type.Type -> VHDLState (Maybe (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
597 construct_vhdl_ty ty = do
598 case Type.splitTyConApp_maybe ty of
599 Just (tycon, args) -> do
600 let name = Name.getOccString (TyCon.tyConName tycon)
603 res <- mk_vector_ty (tfvec_len ty) (tfvec_elem ty)
604 return $ Just $ (Arrow.second Right) res
606 -- res <- mk_vector_ty (sized_word_len ty) ty
607 -- return $ Just $ (Arrow.second Left) res
609 res <- mk_natural_ty 0 (ranged_word_bound ty)
610 return $ Just $ (Arrow.second Right) res
611 -- Create a custom type from this tycon
612 otherwise -> mk_tycon_ty tycon args
613 Nothing -> return $ Nothing
615 -- | Create VHDL type for a custom tycon
616 mk_tycon_ty :: TyCon.TyCon -> [Type.Type] -> VHDLState (Maybe (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
617 mk_tycon_ty tycon args =
618 case TyCon.tyConDataCons tycon of
619 -- Not an algebraic type
620 [] -> error $ "Only custom algebraic types are supported: " ++ (showSDoc $ ppr tycon)
622 let arg_tys = DataCon.dataConRepArgTys dc
623 -- TODO: CoreSubst docs say each Subs can be applied only once. Is this a
624 -- violation? Or does it only mean not to apply it again to the same
626 let real_arg_tys = map (CoreSubst.substTy subst) arg_tys
627 elem_tys <- mapM vhdl_ty real_arg_tys
628 let elems = zipWith AST.ElementDec recordlabels elem_tys
629 -- For a single construct datatype, build a record with one field for
631 -- TODO: Add argument type ids to this, to ensure uniqueness
632 -- TODO: Special handling for tuples?
633 let ty_id = mkVHDLExtId $ nameToString (TyCon.tyConName tycon)
634 let ty_def = AST.TDR $ AST.RecordTypeDef elems
635 return $ Just (ty_id, Left ty_def)
636 dcs -> error $ "Only single constructor datatypes supported: " ++ (showSDoc $ ppr tycon)
638 -- Create a subst that instantiates all types passed to the tycon
639 -- TODO: I'm not 100% sure that this is the right way to do this. It seems
640 -- to work so far, though..
641 tyvars = TyCon.tyConTyVars tycon
642 subst = CoreSubst.extendTvSubstList CoreSubst.emptySubst (zip tyvars args)
644 -- | Create a VHDL vector type
646 Int -- ^ The length of the vector
647 -> Type.Type -- ^ The Haskell element type of the Vector
648 -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
650 mk_vector_ty len el_ty = do
651 elem_types_map <- getA vsElemTypes
652 el_ty_tm <- vhdl_ty el_ty
653 let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len)
654 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
655 let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map
656 case existing_elem_ty of
658 let ty_def = AST.SubtypeIn t (Just range)
659 return (ty_id, ty_def)
661 let vec_id = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId el_ty_tm)
662 let vec_def = AST.TDA $ AST.UnconsArrayDef [tfvec_indexTM] el_ty_tm
663 modA vsElemTypes (Map.insert (OrdType el_ty) (vec_id, vec_def))
664 modA vsTypeFuns (Map.insert (OrdType el_ty) (genUnconsVectorFuns el_ty_tm vec_id))
665 let ty_def = AST.SubtypeIn vec_id (Just range)
666 return (ty_id, ty_def)
669 Int -- ^ The minimum bound (> 0)
670 -> Int -- ^ The maximum bound (> minimum bound)
671 -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
672 mk_natural_ty min_bound max_bound = do
673 let ty_id = mkVHDLExtId $ "nat_" ++ (show min_bound) ++ "_to_" ++ (show max_bound)
674 let range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit $ (show min_bound)) (AST.PrimLit $ (show max_bound))
675 let ty_def = AST.SubtypeIn naturalTM (Just range)
676 return (ty_id, ty_def)
680 ("Bit", std_logic_ty),
681 ("Bool", bool_ty) -- TysWiredIn.boolTy
685 -- Can only contain alphanumerics and underscores. The supplied string must be
686 -- a valid basic id, otherwise an error value is returned. This function is
687 -- not meant to be passed identifiers from a source file, use mkVHDLExtId for
689 mkVHDLBasicId :: String -> AST.VHDLId
691 AST.unsafeVHDLBasicId $ (strip_multiscore . strip_leading . strip_invalid) s
693 -- Strip invalid characters.
694 strip_invalid = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.")
695 -- Strip leading numbers and underscores
696 strip_leading = dropWhile (`elem` ['0'..'9'] ++ "_")
697 -- Strip multiple adjacent underscores
698 strip_multiscore = concat . map (\cs ->
704 -- Shortcut for Extended VHDL Id's. These Id's can contain a lot more
705 -- different characters than basic ids, but can never be used to refer to
707 -- Use extended Ids for any values that are taken from the source file.
708 mkVHDLExtId :: String -> AST.VHDLId
710 AST.unsafeVHDLExtId $ strip_invalid s
712 -- Allowed characters, taken from ForSyde's mkVHDLExtId
713 allowed = ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ " \"#&\\'()*+,./:;<=>_|!$%@?[]^`{}~-"
714 strip_invalid = filter (`elem` allowed)
716 -- Creates a VHDL Id from a binder
721 bndrToVHDLId = mkVHDLExtId . OccName.occNameString . Name.nameOccName . Var.varName
723 -- Extracts the binder name as a String
727 bndrToString = OccName.occNameString . Name.nameOccName . Var.varName
729 -- Get the string version a Var's unique
730 varToStringUniq = show . Var.varUnique
732 -- Extracts the string version of the name
733 nameToString :: Name.Name -> String
734 nameToString = OccName.occNameString . Name.nameOccName
736 recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z']
738 -- | Map a port specification of a builtin function to a VHDL Signal to put in
740 toVHDLSignalMapElement :: (String, AST.TypeMark) -> VHDLSignalMapElement
741 toVHDLSignalMapElement (name, ty) = Just (mkVHDLBasicId name, ty)