1 module Main(main) where
4 import qualified CoreUtils
8 import qualified DataCon
10 import qualified Module
11 import qualified Control.Monad.State as State
14 import NameEnv ( lookupNameEnv )
15 import HscTypes ( cm_binds, cm_types )
16 import MonadUtils ( liftIO )
17 import Outputable ( showSDoc, ppr )
18 import GHC.Paths ( libdir )
19 import DynFlags ( defaultDynFlags )
22 import qualified Monad
24 -- The following modules come from the ForSyDe project. They are really
25 -- internal modules, so ForSyDe.cabal has to be modified prior to installing
26 -- ForSyDe to get access to these modules.
27 import qualified ForSyDe.Backend.VHDL.AST as AST
28 import qualified ForSyDe.Backend.VHDL.Ppr
29 import qualified ForSyDe.Backend.VHDL.FileIO
30 import qualified ForSyDe.Backend.Ppr
31 -- This is needed for rendering the pretty printed VHDL
32 import Text.PrettyPrint.HughesPJ (render)
36 defaultErrorHandler defaultDynFlags $ do
37 runGhc (Just libdir) $ do
38 dflags <- getSessionDynFlags
39 setSessionDynFlags dflags
40 --target <- guessTarget "adder.hs" Nothing
41 --liftIO (print (showSDoc (ppr (target))))
42 --liftIO $ printTarget target
45 --core <- GHC.compileToCoreSimplified "Adders.hs"
46 core <- GHC.compileToCoreSimplified "Adders.hs"
47 --liftIO $ printBinds (cm_binds core)
48 let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["dff"]
49 liftIO $ printBinds binds
50 -- Turn bind into VHDL
51 let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession 0 [])
52 liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl
53 liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl"
54 liftIO $ putStr $ "\n\nFinal session:\n" ++ show sess
57 -- Turns the given bind into VHDL
59 -- Add the builtin functions
60 mapM (uncurry addFunc) builtin_funcs
61 -- Create entities and architectures for them
62 units <- mapM expandBind binds
63 return $ AST.DesignFile
67 printTarget (Target (TargetFile file (Just x)) obj Nothing) =
70 printBinds [] = putStr "done\n\n"
71 printBinds (b:bs) = do
76 printBind (NonRec b expr) = do
80 printBind (Rec binds) = do
82 foldl1 (>>) (map printBind' binds)
84 printBind' (b, expr) = do
85 putStr $ getOccString b
86 putStr $ showSDoc $ ppr expr
89 findBind :: [CoreBind] -> String -> Maybe CoreBind
90 findBind binds lookfor =
91 -- This ignores Recs and compares the name of the bind with lookfor,
92 -- disregarding any namespaces in OccName and extra attributes in Name and
96 NonRec var _ -> lookfor == (occNameString $ nameOccName $ getName var)
100 SignalNameMap -- The port name to bind to
102 -- The signal or port to bind to it
103 -> AST.AssocElem -- The resulting port map entry
105 -- Accepts a port name and an argument to map to it.
106 -- Returns the appropriate line for in the port map
107 getPortMapEntry (Single (portname, _)) (Single (signame, _)) =
108 (Just portname) AST.:=>: (AST.ADName (AST.NSimple signame))
110 [(CoreBndr, SignalNameMap)]
111 -- A list of bindings in effect
112 -> CoreExpr -- The expression to expand
114 [AST.SigDec], -- Needed signal declarations
115 [AST.ConcSm], -- Needed component instantations and
116 -- signal assignments.
117 [SignalNameMap], -- The signal names corresponding to
118 -- the expression's arguments
119 SignalNameMap) -- The signal names corresponding to
120 -- the expression's result.
121 expandExpr binds lam@(Lam b expr) = do
122 -- Generate a new signal to which we will expect this argument to be bound.
123 signal_name <- uniqueName ("arg_" ++ getOccString b)
124 -- Find the type of the binder
125 let (arg_ty, _) = Type.splitFunTy (CoreUtils.exprType lam)
126 -- Create signal names for the binder
127 -- TODO: We assume arguments are ports here
128 let arg_signal = getPortNameMapForTy ("xxx") arg_ty (useAsPort arg_ty)
129 -- Create the corresponding signal declarations
130 let signal_decls = mkSignalsFromMap arg_signal
131 -- Add the binder to the list of binds
132 let binds' = (b, arg_signal) : binds
133 -- Expand the rest of the expression
134 (signal_decls', statements', arg_signals', res_signal') <- expandExpr binds' expr
135 -- Properly merge the results
136 return (signal_decls ++ signal_decls',
138 arg_signal : arg_signals',
141 expandExpr binds (Var id) =
142 return ([], [], [], bind)
144 -- Lookup the id in our binds map
145 bind = Maybe.fromMaybe
146 (error $ "Argument " ++ getOccString id ++ "is unknown")
149 expandExpr binds l@(Let (NonRec b bexpr) expr) = do
150 (signal_decls, statements, arg_signals, res_signals) <- expandExpr binds bexpr
151 let binds' = (b, res_signals) : binds
152 (signal_decls', statements', arg_signals', res_signals') <- expandExpr binds' expr
154 signal_decls ++ signal_decls',
155 statements ++ statements',
159 expandExpr binds app@(App _ _) = do
160 -- Is this a data constructor application?
161 case CoreUtils.exprIsConApp_maybe app of
162 -- Is this a tuple construction?
163 Just (dc, args) -> if DataCon.isTupleCon dc
165 expandBuildTupleExpr binds (dataConAppArgs dc args)
167 error "Data constructors other than tuples not supported"
169 -- Normal function application, should map to a component instantiation
170 let ((Var f), args) = collectArgs app in
171 expandApplicationExpr binds (CoreUtils.exprType app) f args
173 expandExpr binds expr@(Case (Var v) b _ alts) =
175 [alt] -> expandSingleAltCaseExpr binds v b alt
176 otherwise -> error $ "Multiple alternative case expression not supported: " ++ (showSDoc $ ppr expr)
178 expandExpr binds expr@(Case _ b _ _) =
179 error $ "Case expression with non-variable scrutinee not supported: " ++ (showSDoc $ ppr expr)
181 expandExpr binds expr =
182 error $ "Unsupported expression: " ++ (showSDoc $ ppr $ expr)
184 -- Expands the construction of a tuple into VHDL
185 expandBuildTupleExpr ::
186 [(CoreBndr, SignalNameMap)]
187 -- A list of bindings in effect
188 -> [CoreExpr] -- A list of expressions to put in the tuple
189 -> VHDLState ( [AST.SigDec], [AST.ConcSm], [SignalNameMap], SignalNameMap)
191 expandBuildTupleExpr binds args = do
192 -- Split the tuple constructor arguments into types and actual values.
193 -- Expand each of the values in the tuple
194 (signals_declss, statementss, arg_signalss, res_signals) <-
195 (Monad.liftM List.unzip4) $ mapM (expandExpr binds) args
196 if any (not . null) arg_signalss
197 then error "Putting high order functions in tuples not supported"
200 concat signals_declss,
205 -- Expands the most simple case expression that scrutinizes a plain variable
206 -- and has a single alternative. This simple form currently allows only for
207 -- unpacking tuple variables.
208 expandSingleAltCaseExpr ::
209 [(CoreBndr, SignalNameMap)]
210 -- A list of bindings in effect
211 -> Var.Var -- The scrutinee
212 -> CoreBndr -- The binder to bind the scrutinee to
213 -> CoreAlt -- The single alternative
214 -> VHDLState ( [AST.SigDec], [AST.ConcSm], [SignalNameMap], SignalNameMap)
217 expandSingleAltCaseExpr binds v b alt@(DataAlt datacon, bind_vars, expr) =
218 if not (DataCon.isTupleCon datacon)
220 error $ "Dataconstructors other than tuple constructors not supported in case pattern of alternative: " ++ (showSDoc $ ppr alt)
223 -- Lookup the scrutinee (which must be a variable bound to a tuple) in
224 -- the existing bindings list and get the portname map for each of
226 Tuple tuple_ports = Maybe.fromMaybe
227 (error $ "Case expression uses unknown scrutinee " ++ getOccString v)
229 -- TODO include b in the binds list
230 -- Merge our existing binds with the new binds.
231 binds' = (zip bind_vars tuple_ports) ++ binds
233 -- Expand the expression with the new binds list
234 expandExpr binds' expr
236 expandSingleAltCaseExpr _ _ _ alt =
237 error $ "Case patterns other than data constructors not supported in case alternative: " ++ (showSDoc $ ppr alt)
240 -- Expands the application of argument to a function into VHDL
241 expandApplicationExpr ::
242 [(CoreBndr, SignalNameMap)]
243 -- A list of bindings in effect
244 -> Type -- The result type of the function call
245 -> Var.Var -- The function to call
246 -> [CoreExpr] -- A list of argumetns to apply to the function
247 -> VHDLState ( [AST.SigDec], [AST.ConcSm], [SignalNameMap], SignalNameMap)
249 expandApplicationExpr binds ty f args = do
250 let name = getOccString f
251 -- Generate a unique name for the application
252 appname <- uniqueName ("app_" ++ name)
253 -- Lookup the hwfunction to instantiate
254 HWFunction vhdl_id inports outport <- getHWFunc (appToHsFunction f args ty)
255 -- Expand each of the args, so each of them is reduced to output signals
256 (arg_signal_decls, arg_statements, arg_res_signals) <- expandArgs binds args
257 -- Bind each of the input ports to the expanded arguments
258 let inmaps = concat $ zipWith createAssocElems inports arg_res_signals
259 -- Create signal names for our result
260 -- TODO: We assume the result is a port here
261 let res_signal = getPortNameMapForTy (appname ++ "_out") ty (useAsPort ty)
262 -- Create the corresponding signal declarations
263 let signal_decls = mkSignalsFromMap res_signal
264 -- Bind each of the output ports to our output signals
265 let outmaps = mapOutputPorts outport res_signal
266 -- Instantiate the component
267 let component = AST.CSISm $ AST.CompInsSm
268 (AST.unsafeVHDLBasicId appname)
269 (AST.IUEntity (AST.NSimple vhdl_id))
270 (AST.PMapAspect (inmaps ++ outmaps))
271 -- Merge the generated declarations
273 signal_decls ++ arg_signal_decls,
274 component : arg_statements,
275 [], -- We don't take any extra arguments; we don't support higher order functions yet
278 -- Creates a list of AssocElems (port map lines) that maps the given signals
279 -- to the given ports.
281 SignalNameMap -- The port names to bind to
282 -> SignalNameMap -- The signals to bind to it
283 -> [AST.AssocElem] -- The resulting port map lines
285 createAssocElems (Single (port_id, _)) (Single (signal_id, _)) =
286 [(Just port_id) AST.:=>: (AST.ADName (AST.NSimple signal_id))]
288 createAssocElems (Tuple ports) (Tuple signals) =
289 concat $ zipWith createAssocElems ports signals
291 -- Generate a signal declaration for a signal with the given name and the
292 -- given type and no value. Also returns the id of the signal.
293 mkSignal :: String -> AST.TypeMark -> (AST.VHDLId, AST.SigDec)
295 (id, mkSignalFromId id ty)
297 id = AST.unsafeVHDLBasicId name
299 mkSignalFromId :: AST.VHDLId -> AST.TypeMark -> AST.SigDec
300 mkSignalFromId id ty =
301 AST.SigDec id ty Nothing
303 -- Generates signal declarations for all the signals in the given map
308 mkSignalsFromMap (Single (id, ty)) =
309 [mkSignalFromId id ty]
311 mkSignalsFromMap (Tuple signals) =
312 concat $ map mkSignalsFromMap signals
315 [(CoreBndr, SignalNameMap)] -- A list of bindings in effect
316 -> [CoreExpr] -- The arguments to expand
317 -> VHDLState ([AST.SigDec], [AST.ConcSm], [SignalNameMap])
318 -- The resulting signal declarations,
319 -- component instantiations and a
320 -- VHDLName for each of the
321 -- expressions passed in.
322 expandArgs binds (e:exprs) = do
323 -- Expand the first expression
324 (signal_decls, statements, arg_signals, res_signal) <- expandExpr binds e
325 if not (null arg_signals)
326 then error $ "Passing functions as arguments not supported: " ++ (showSDoc $ ppr e)
328 (signal_decls', statements', res_signals') <- expandArgs binds exprs
330 signal_decls ++ signal_decls',
331 statements ++ statements',
332 res_signal : res_signals')
334 expandArgs _ [] = return ([], [], [])
336 -- Extract the arguments from a data constructor application (that is, the
337 -- normal args, leaving out the type args).
338 dataConAppArgs :: DataCon -> [CoreExpr] -> [CoreExpr]
339 dataConAppArgs dc args =
342 tycount = length $ DataCon.dataConAllTyVars dc
345 SignalNameMap -- The output portnames of the component
346 -> SignalNameMap -- The output portnames and/or signals to map these to
347 -> [AST.AssocElem] -- The resulting output ports
349 -- Map the output port of a component to the output port of the containing
351 mapOutputPorts (Single (portname, _)) (Single (signalname, _)) =
352 [(Just portname) AST.:=>: (AST.ADName (AST.NSimple signalname))]
354 -- Map matching output ports in the tuple
355 mapOutputPorts (Tuple ports) (Tuple signals) =
356 concat (zipWith mapOutputPorts ports signals)
359 CoreBind -- The binder to expand into VHDL
360 -> VHDLState [AST.LibraryUnit] -- The resulting VHDL
362 expandBind (Rec _) = error "Recursive binders not supported"
364 expandBind bind@(NonRec var expr) = do
365 -- Create the function signature
366 let ty = CoreUtils.exprType expr
367 let hsfunc = mkHsFunction var ty
368 hwfunc <- mkHWFunction bind hsfunc
369 -- Add it to the session
370 addFunc hsfunc hwfunc
371 arch <- getArchitecture hwfunc expr
372 let entity = getEntity hwfunc
378 HWFunction -- The function to generate an architecture for
379 -> CoreExpr -- The expression that is bound to the function
380 -> VHDLState AST.ArchBody -- The resulting architecture
382 getArchitecture hwfunc expr = do
384 let HWFunction vhdl_id inports outport = hwfunc
385 -- Expand the expression into an architecture body
386 (signal_decls, statements, arg_signals, res_signal) <- expandExpr [] expr
387 let inport_assigns = concat $ zipWith createSignalAssignments arg_signals inports
388 let outport_assigns = createSignalAssignments outport res_signal
389 return $ AST.ArchBody
390 (AST.unsafeVHDLBasicId "structural")
391 (AST.NSimple vhdl_id)
392 (map AST.BDISD signal_decls)
393 (inport_assigns ++ outport_assigns ++ statements)
395 -- Generate a VHDL entity declaration for the given function
396 getEntity :: HWFunction -> AST.EntityDec
397 getEntity (HWFunction vhdl_id inports outport) =
398 AST.EntityDec vhdl_id ports
401 (concat $ map (mkIfaceSigDecs AST.In) inports)
402 ++ mkIfaceSigDecs AST.Out outport
405 AST.Mode -- The port's mode (In or Out)
406 -> SignalNameMap -- The ports to generate a map for
407 -> [AST.IfaceSigDec] -- The resulting ports
409 mkIfaceSigDecs mode (Single (port_id, ty)) =
410 [AST.IfaceSigDec port_id mode ty]
412 mkIfaceSigDecs mode (Tuple ports) =
413 concat $ map (mkIfaceSigDecs mode) ports
415 -- Unused values (state) don't generate ports
416 mkIfaceSigDecs mode Unused =
419 -- Create concurrent assignments of one map of signals to another. The maps
420 -- should have a similar form.
421 createSignalAssignments ::
422 SignalNameMap -- The signals to assign to
423 -> SignalNameMap -- The signals to assign
424 -> [AST.ConcSm] -- The resulting assignments
426 -- A simple assignment of one signal to another (greatly complicated because
427 -- signal assignments can be conditional with multiple conditions in VHDL).
428 createSignalAssignments (Single (dst, _)) (Single (src, _)) =
431 src_name = AST.NSimple src
432 src_expr = AST.PrimName src_name
433 src_wform = AST.Wform [AST.WformElem src_expr Nothing]
434 dst_name = (AST.NSimple dst)
435 assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
437 createSignalAssignments (Tuple dsts) (Tuple srcs) =
438 concat $ zipWith createSignalAssignments dsts srcs
440 createSignalAssignments Unused (Single (src, _)) =
444 createSignalAssignments (Single (src, _)) Unused =
448 createSignalAssignments dst src =
449 error $ "Non matching source and destination: " ++ show dst ++ "\nand\n" ++ show src
451 type SignalNameMap = HsValueMap (AST.VHDLId, AST.TypeMark)
453 -- | A datatype that maps each of the single values in a haskell structure to
454 -- a mapto. The map has the same structure as the haskell type mapped, ie
455 -- nested tuples etc.
456 data HsValueMap mapto =
457 Tuple [HsValueMap mapto]
462 -- | Creates a HsValueMap with the same structure as the given type, using the
463 -- given function for mapping the single types.
465 (Type -> HsValueMap mapto) -- ^ A function to map single value Types
466 -- (basically anything but tuples) to a
467 -- HsValueMap (not limited to the Single
469 -> Type -- ^ The type to map to a HsValueMap
470 -> HsValueMap mapto -- ^ The resulting map
473 case Type.splitTyConApp_maybe ty of
474 Just (tycon, args) ->
475 if (TyCon.isTupleTyCon tycon)
477 -- Handle tuple construction especially
478 Tuple (map (mkHsValueMap f) args)
480 -- And let f handle the rest
482 -- And let f handle the rest
485 -- Generate a port name map (or multiple for tuple types) in the given direction for
487 getPortNameMapForTys :: String -> Int -> [Type] -> [HsUseMap] -> [SignalNameMap]
488 getPortNameMapForTys prefix num [] [] = []
489 getPortNameMapForTys prefix num (t:ts) (u:us) =
490 (getPortNameMapForTy (prefix ++ show num) t u) : getPortNameMapForTys prefix (num + 1) ts us
492 getPortNameMapForTy :: String -> Type -> HsUseMap -> SignalNameMap
493 getPortNameMapForTy name _ (Single State) =
496 getPortNameMapForTy name ty use =
497 if (TyCon.isTupleTyCon tycon) then
498 let (Tuple uses) = use in
499 -- Expand tuples we find
500 Tuple (getPortNameMapForTys name 0 args uses)
501 else -- Assume it's a type constructor application, ie simple data type
502 Single ((AST.unsafeVHDLBasicId name), (vhdl_ty ty))
504 (tycon, args) = Type.splitTyConApp ty
506 data HWFunction = HWFunction { -- A function that is available in hardware
507 vhdlId :: AST.VHDLId,
508 inPorts :: [SignalNameMap],
509 outPort :: SignalNameMap
510 --entity :: AST.EntityDec
513 -- Turns a CoreExpr describing a function into a description of its input and
516 CoreBind -- The core binder to generate the interface for
517 -> HsFunction -- The HsFunction describing the function
518 -> VHDLState HWFunction -- The function interface
520 mkHWFunction (NonRec var expr) hsfunc =
521 return $ HWFunction (mkVHDLId name) inports outport
523 name = getOccString var
524 ty = CoreUtils.exprType expr
525 (args, res) = Type.splitFunTys ty
526 inports = case args of
527 -- Handle a single port specially, to prevent an extra 0 in the name
528 [port] -> [getPortNameMapForTy "portin" port (head $ hsArgs hsfunc)]
529 ps -> getPortNameMapForTys "portin" 0 ps (hsArgs hsfunc)
530 outport = getPortNameMapForTy "portout" res (hsRes hsfunc)
532 mkHWFunction (Rec _) _ =
533 error "Recursive binders not supported"
535 -- | How is a given (single) value in a function's type (ie, argument or
536 -- return value) used?
538 Port -- ^ Use it as a port (input or output)
539 | State --- ^ Use it as state (input or output)
542 useAsPort = mkHsValueMap (\x -> Single Port)
543 useAsState = mkHsValueMap (\x -> Single State)
545 type HsUseMap = HsValueMap HsValueUse
547 -- | This type describes a particular use of a Haskell function and is used to
548 -- look up an appropriate hardware description.
549 data HsFunction = HsFunction {
550 hsName :: String, -- ^ What was the name of the original Haskell function?
551 hsArgs :: [HsUseMap], -- ^ How are the arguments used?
552 hsRes :: HsUseMap -- ^ How is the result value used?
553 } deriving (Show, Eq)
555 -- | Translate a function application to a HsFunction. i.e., which function
556 -- do you need to translate this function application.
558 Var.Var -- ^ The function to call
559 -> [CoreExpr] -- ^ The function arguments
560 -> Type -- ^ The return type
561 -> HsFunction -- ^ The needed HsFunction
563 appToHsFunction f args ty =
564 HsFunction hsname hsargs hsres
566 mkPort = \x -> Single Port
567 hsargs = map (mkHsValueMap mkPort . CoreUtils.exprType) args
568 hsres = mkHsValueMap mkPort ty
569 hsname = getOccString f
571 -- | Translate a top level function declaration to a HsFunction. i.e., which
572 -- interface will be provided by this function. This function essentially
573 -- defines the "calling convention" for hardware models.
575 Var.Var -- ^ The function defined
576 -> Type -- ^ The function type (including arguments!)
577 -> HsFunction -- ^ The resulting HsFunction
580 HsFunction hsname hsargs hsres
582 hsname = getOccString f
583 (arg_tys, res_ty) = Type.splitFunTys ty
584 -- The last argument must be state
585 state_ty = last arg_tys
586 state = useAsState state_ty
587 -- All but the last argument are inports
588 inports = map useAsPort (init arg_tys)
589 hsargs = inports ++ [state]
590 hsres = case splitTupleType res_ty of
591 -- Result type must be a two tuple (state, ports)
592 Just [outstate_ty, outport_ty] -> if Type.coreEqType state_ty outstate_ty
594 Tuple [state, useAsPort outport_ty]
596 error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty)
597 otherwise -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports."
599 data VHDLSession = VHDLSession {
600 nameCount :: Int, -- A counter that can be used to generate unique names
601 funcs :: [(HsFunction, HWFunction)] -- All functions available
604 type VHDLState = State.State VHDLSession
606 -- Add the function to the session
607 addFunc :: HsFunction -> HWFunction -> VHDLState ()
608 addFunc hsfunc hwfunc = do
609 fs <- State.gets funcs -- Get the funcs element from the session
610 State.modify (\x -> x {funcs = (hsfunc, hwfunc) : fs }) -- Prepend name and f
612 -- Lookup the function with the given name in the current session. Errors if
614 getHWFunc :: HsFunction -> VHDLState HWFunction
615 getHWFunc hsfunc = do
616 fs <- State.gets funcs -- Get the funcs element from the session
617 return $ Maybe.fromMaybe
618 (error $ "Function " ++ (hsName hsfunc) ++ "is unknown? This should not happen!")
621 -- | Splits a tuple type into a list of element types, or Nothing if the type
622 -- is not a tuple type.
624 Type -- ^ The type to split
625 -> Maybe [Type] -- ^ The tuples element types
628 case Type.splitTyConApp_maybe ty of
629 Just (tycon, args) -> if TyCon.isTupleTyCon tycon
636 -- Makes the given name unique by appending a unique number.
637 -- This does not do any checking against existing names, so it only guarantees
638 -- uniqueness with other names generated by uniqueName.
639 uniqueName :: String -> VHDLState String
641 count <- State.gets nameCount -- Get the funcs element from the session
642 State.modify (\s -> s {nameCount = count + 1})
643 return $ name ++ "_" ++ (show count)
646 mkVHDLId :: String -> AST.VHDLId
647 mkVHDLId = AST.unsafeVHDLBasicId
651 (HsFunction "hwxor" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwxor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))),
652 (HsFunction "hwand" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwand") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))),
653 (HsFunction "hwor" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))),
654 (HsFunction "hwnot" [(Single Port)] (Single Port), HWFunction (mkVHDLId "hwnot") [Single (mkVHDLId "i", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty)))
657 vhdl_bit_ty :: AST.TypeMark
658 vhdl_bit_ty = AST.unsafeVHDLBasicId "Bit"
660 -- Translate a Haskell type to a VHDL type
661 vhdl_ty :: Type -> AST.TypeMark
662 vhdl_ty ty = Maybe.fromMaybe
663 (error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty))
666 -- Translate a Haskell type to a VHDL type
667 vhdl_ty_maybe :: Type -> Maybe AST.TypeMark
669 case Type.splitTyConApp_maybe ty of
670 Just (tycon, args) ->
671 let name = TyCon.tyConName tycon in
672 -- TODO: Do something more robust than string matching
673 case getOccString name of
674 "Bit" -> Just vhdl_bit_ty
678 -- vim: set ts=8 sw=2 sts=2 expandtab: