1 module Translator where
2 import GHC hiding (loadModule, sigName)
4 import qualified CoreUtils
8 import qualified DataCon
10 import qualified Module
11 import qualified Control.Monad.State as State
13 import qualified Data.Map as Map
15 import NameEnv ( lookupNameEnv )
16 import qualified HscTypes
17 import HscTypes ( cm_binds, cm_types )
18 import MonadUtils ( liftIO )
19 import Outputable ( showSDoc, ppr )
20 import GHC.Paths ( libdir )
21 import DynFlags ( defaultDynFlags )
24 import qualified Monad
26 -- The following modules come from the ForSyDe project. They are really
27 -- internal modules, so ForSyDe.cabal has to be modified prior to installing
28 -- ForSyDe to get access to these modules.
29 import qualified ForSyDe.Backend.VHDL.AST as AST
30 import qualified ForSyDe.Backend.VHDL.Ppr
31 import qualified ForSyDe.Backend.VHDL.FileIO
32 import qualified ForSyDe.Backend.Ppr
33 -- This is needed for rendering the pretty printed VHDL
34 import Text.PrettyPrint.HughesPJ (render)
36 import TranslatorTypes
45 makeVHDL "Alu.hs" "register_bank"
47 makeVHDL :: String -> String -> IO ()
48 makeVHDL filename name = do
50 core <- loadModule filename
52 vhdl <- moduleToVHDL core [name]
54 writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
56 -- | Show the core structure of the given binds in the given file.
57 listBind :: String -> String -> IO ()
58 listBind filename name = do
59 core <- loadModule filename
60 let binds = findBinds core [name]
62 putStr $ prettyShow binds
63 putStr $ showSDoc $ ppr binds
66 -- | Translate the binds with the given names from the given core module to
68 moduleToVHDL :: HscTypes.CoreModule -> [String] -> IO AST.DesignFile
69 moduleToVHDL core names = do
70 --liftIO $ putStr $ prettyShow (cm_binds core)
71 let binds = findBinds core names
72 --putStr $ prettyShow binds
73 -- Turn bind into VHDL
74 let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
75 putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl
76 putStr $ "\n\nFinal session:\n" ++ prettyShow sess ++ "\n\n"
80 -- Turns the given bind into VHDL
82 -- Add the builtin functions
83 mapM addBuiltIn builtin_funcs
84 -- Create entities and architectures for them
85 mapM processBind binds
86 modFuncs nameFlatFunction
87 modFuncs VHDL.createEntity
88 modFuncs VHDL.createArchitecture
91 -- | Write the given design file to the given file
92 writeVHDL :: AST.DesignFile -> String -> IO ()
93 writeVHDL = ForSyDe.Backend.VHDL.FileIO.writeDesignFile
95 -- | Loads the given file and turns it into a core module.
96 loadModule :: String -> IO HscTypes.CoreModule
98 defaultErrorHandler defaultDynFlags $ do
99 runGhc (Just libdir) $ do
100 dflags <- getSessionDynFlags
101 setSessionDynFlags dflags
102 --target <- guessTarget "adder.hs" Nothing
103 --liftIO (print (showSDoc (ppr (target))))
104 --liftIO $ printTarget target
105 --setTargets [target]
106 --load LoadAllTargets
107 --core <- GHC.compileToCoreSimplified "Adders.hs"
108 core <- GHC.compileToCoreSimplified filename
111 -- | Extracts the named binds from the given module.
112 findBinds :: HscTypes.CoreModule -> [String] -> [CoreBind]
113 findBinds core names = Maybe.mapMaybe (findBind (cm_binds core)) names
115 -- | Extract a named bind from the given list of binds
116 findBind :: [CoreBind] -> String -> Maybe CoreBind
117 findBind binds lookfor =
118 -- This ignores Recs and compares the name of the bind with lookfor,
119 -- disregarding any namespaces in OccName and extra attributes in Name and
121 find (\b -> case b of
123 NonRec var _ -> lookfor == (occNameString $ nameOccName $ getName var)
126 -- | Processes the given bind as a top level bind.
128 CoreBind -- The bind to process
131 processBind (Rec _) = error "Recursive binders not supported"
132 processBind bind@(NonRec var expr) = do
133 -- Create the function signature
134 let ty = CoreUtils.exprType expr
135 let hsfunc = mkHsFunction var ty
136 flattenBind hsfunc bind
138 -- | Flattens the given bind into the given signature and adds it to the
139 -- session. Then (recursively) finds any functions it uses and does the same
142 HsFunction -- The signature to flatten into
143 -> CoreBind -- The bind to flatten
146 flattenBind _ (Rec _) = error "Recursive binders not supported"
148 flattenBind hsfunc bind@(NonRec var expr) = do
149 -- Flatten the function
150 let flatfunc = flattenFunction hsfunc bind
152 setFlatFunc hsfunc flatfunc
153 let used_hsfuncs = Maybe.mapMaybe usedHsFunc (flat_defs flatfunc)
154 State.mapM resolvFunc used_hsfuncs
157 -- | Find the given function, flatten it and add it to the session. Then
158 -- (recursively) do the same for any functions used.
160 HsFunction -- | The function to look for
163 resolvFunc hsfunc = do
164 -- See if the function is already known
165 func <- getFunc hsfunc
167 -- Already known, do nothing
170 -- New function, resolve it
172 -- Get the current module
174 -- Find the named function
175 let bind = findBind (cm_binds core) name
177 Nothing -> error $ "Couldn't find function " ++ name ++ " in current module."
178 Just b -> flattenBind hsfunc b
180 name = hsFuncName hsfunc
182 -- | Translate a top level function declaration to a HsFunction. i.e., which
183 -- interface will be provided by this function. This function essentially
184 -- defines the "calling convention" for hardware models.
186 Var.Var -- ^ The function defined
187 -> Type -- ^ The function type (including arguments!)
188 -> HsFunction -- ^ The resulting HsFunction
191 HsFunction hsname hsargs hsres
193 hsname = getOccString f
194 (arg_tys, res_ty) = Type.splitFunTys ty
195 -- The last argument must be state
196 state_ty = last arg_tys
197 state = useAsState (mkHsValueMap state_ty)
198 -- All but the last argument are inports
199 inports = map (useAsPort . mkHsValueMap)(init arg_tys)
200 hsargs = inports ++ [state]
201 hsres = case splitTupleType res_ty of
202 -- Result type must be a two tuple (state, ports)
203 Just [outstate_ty, outport_ty] -> if Type.coreEqType state_ty outstate_ty
205 Tuple [state, useAsPort (mkHsValueMap outport_ty)]
207 error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty)
208 otherwise -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports."
210 -- | Adds signal names to the given FlatFunction
216 nameFlatFunction hsfunc fdata =
217 let func = flatFunc fdata in
219 -- Skip (builtin) functions without a FlatFunction
220 Nothing -> do return ()
221 -- Name the signals in all other functions
223 let s = flat_sigs flatfunc in
224 let s' = map nameSignal s in
225 let flatfunc' = flatfunc { flat_sigs = s' } in
226 setFlatFunc hsfunc flatfunc'
228 nameSignal :: (SignalId, SignalInfo) -> (SignalId, SignalInfo)
229 nameSignal (id, info) =
230 let hints = nameHints info in
231 let parts = ("sig" : hints) ++ [show id] in
232 let name = concat $ List.intersperse "_" parts in
233 (id, info {sigName = Just name})
235 -- | Splits a tuple type into a list of element types, or Nothing if the type
236 -- is not a tuple type.
238 Type -- ^ The type to split
239 -> Maybe [Type] -- ^ The tuples element types
242 case Type.splitTyConApp_maybe ty of
243 Just (tycon, args) -> if TyCon.isTupleTyCon tycon
250 -- | A consise representation of a (set of) ports on a builtin function
251 type PortMap = HsValueMap (String, AST.TypeMark)
252 -- | A consise representation of a builtin function
253 data BuiltIn = BuiltIn String [PortMap] PortMap
255 -- | Map a port specification of a builtin function to a VHDL Signal to put in
257 toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
258 toVHDLSignalMap = fmap (\(name, ty) -> Just (VHDL.mkVHDLId name, ty))
260 -- | Translate a concise representation of a builtin function to something
261 -- that can be put into FuncMap directly.
262 addBuiltIn :: BuiltIn -> VHDLState ()
263 addBuiltIn (BuiltIn name args res) = do
265 setEntity hsfunc entity
267 hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
268 entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
272 BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
273 BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
274 BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
275 BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
278 -- vim: set ts=8 sw=2 sts=2 expandtab: