1 module Translator where
2 import GHC hiding (loadModule, sigName)
4 import qualified CoreUtils
8 import qualified DataCon
10 import qualified Module
11 import qualified Control.Monad.State as State
13 import qualified Data.Map as Map
15 import NameEnv ( lookupNameEnv )
16 import qualified HscTypes
17 import HscTypes ( cm_binds, cm_types )
18 import MonadUtils ( liftIO )
19 import Outputable ( showSDoc, ppr )
20 import GHC.Paths ( libdir )
21 import DynFlags ( defaultDynFlags )
24 import qualified Monad
26 -- The following modules come from the ForSyDe project. They are really
27 -- internal modules, so ForSyDe.cabal has to be modified prior to installing
28 -- ForSyDe to get access to these modules.
29 import qualified ForSyDe.Backend.VHDL.AST as AST
30 import qualified ForSyDe.Backend.VHDL.Ppr
31 import qualified ForSyDe.Backend.VHDL.FileIO
32 import qualified ForSyDe.Backend.Ppr
33 -- This is needed for rendering the pretty printed VHDL
34 import Text.PrettyPrint.HughesPJ (render)
36 import TranslatorTypes
45 makeVHDL "Alu.hs" "register_bank"
47 makeVHDL :: String -> String -> IO ()
48 makeVHDL filename name = do
50 core <- loadModule filename
52 vhdl <- moduleToVHDL core [name]
54 mapM (writeVHDL "../vhdl/vhdl/") vhdl
57 -- | Show the core structure of the given binds in the given file.
58 listBind :: String -> String -> IO ()
59 listBind filename name = do
60 core <- loadModule filename
61 let binds = findBinds core [name]
63 putStr $ prettyShow binds
64 putStr $ showSDoc $ ppr binds
67 -- | Translate the binds with the given names from the given core module to
69 moduleToVHDL :: HscTypes.CoreModule -> [String] -> IO [AST.DesignFile]
70 moduleToVHDL core names = do
71 --liftIO $ putStr $ prettyShow (cm_binds core)
72 let binds = findBinds core names
73 --putStr $ prettyShow binds
74 -- Turn bind into VHDL
75 let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
76 mapM (putStr . render . ForSyDe.Backend.Ppr.ppr) vhdl
77 putStr $ "\n\nFinal session:\n" ++ prettyShow sess ++ "\n\n"
81 -- Turns the given bind into VHDL
83 -- Add the builtin functions
84 mapM addBuiltIn builtin_funcs
85 -- Create entities and architectures for them
86 mapM processBind binds
87 modFuncs nameFlatFunction
88 modFuncs VHDL.createEntity
89 modFuncs VHDL.createArchitecture
92 -- | Write the given design file to a file inside the given dir
93 -- The first library unit in the designfile must be an entity, whose name
94 -- will be used as a filename.
95 writeVHDL :: String -> AST.DesignFile -> IO ()
96 writeVHDL dir vhdl = do
97 let AST.DesignFile _ (u:us) = vhdl
98 let AST.LUEntity (AST.EntityDec id _) = u
99 let fname = dir ++ AST.fromVHDLId id ++ ".vhdl"
100 ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl fname
102 -- | Loads the given file and turns it into a core module.
103 loadModule :: String -> IO HscTypes.CoreModule
104 loadModule filename =
105 defaultErrorHandler defaultDynFlags $ do
106 runGhc (Just libdir) $ do
107 dflags <- getSessionDynFlags
108 setSessionDynFlags dflags
109 --target <- guessTarget "adder.hs" Nothing
110 --liftIO (print (showSDoc (ppr (target))))
111 --liftIO $ printTarget target
112 --setTargets [target]
113 --load LoadAllTargets
114 --core <- GHC.compileToCoreSimplified "Adders.hs"
115 core <- GHC.compileToCoreSimplified filename
118 -- | Extracts the named binds from the given module.
119 findBinds :: HscTypes.CoreModule -> [String] -> [CoreBind]
120 findBinds core names = Maybe.mapMaybe (findBind (cm_binds core)) names
122 -- | Extract a named bind from the given list of binds
123 findBind :: [CoreBind] -> String -> Maybe CoreBind
124 findBind binds lookfor =
125 -- This ignores Recs and compares the name of the bind with lookfor,
126 -- disregarding any namespaces in OccName and extra attributes in Name and
128 find (\b -> case b of
130 NonRec var _ -> lookfor == (occNameString $ nameOccName $ getName var)
133 -- | Processes the given bind as a top level bind.
135 CoreBind -- The bind to process
138 processBind (Rec _) = error "Recursive binders not supported"
139 processBind bind@(NonRec var expr) = do
140 -- Create the function signature
141 let ty = CoreUtils.exprType expr
142 let hsfunc = mkHsFunction var ty
143 flattenBind hsfunc bind
145 -- | Flattens the given bind into the given signature and adds it to the
146 -- session. Then (recursively) finds any functions it uses and does the same
149 HsFunction -- The signature to flatten into
150 -> CoreBind -- The bind to flatten
153 flattenBind _ (Rec _) = error "Recursive binders not supported"
155 flattenBind hsfunc bind@(NonRec var expr) = do
156 -- Flatten the function
157 let flatfunc = flattenFunction hsfunc bind
159 setFlatFunc hsfunc flatfunc
160 let used_hsfuncs = Maybe.mapMaybe usedHsFunc (flat_defs flatfunc)
161 State.mapM resolvFunc used_hsfuncs
164 -- | Find the given function, flatten it and add it to the session. Then
165 -- (recursively) do the same for any functions used.
167 HsFunction -- | The function to look for
170 resolvFunc hsfunc = do
171 -- See if the function is already known
172 func <- getFunc hsfunc
174 -- Already known, do nothing
177 -- New function, resolve it
179 -- Get the current module
181 -- Find the named function
182 let bind = findBind (cm_binds core) name
184 Nothing -> error $ "Couldn't find function " ++ name ++ " in current module."
185 Just b -> flattenBind hsfunc b
187 name = hsFuncName hsfunc
189 -- | Translate a top level function declaration to a HsFunction. i.e., which
190 -- interface will be provided by this function. This function essentially
191 -- defines the "calling convention" for hardware models.
193 Var.Var -- ^ The function defined
194 -> Type -- ^ The function type (including arguments!)
195 -> HsFunction -- ^ The resulting HsFunction
198 HsFunction hsname hsargs hsres
200 hsname = getOccString f
201 (arg_tys, res_ty) = Type.splitFunTys ty
202 -- The last argument must be state
203 state_ty = last arg_tys
204 state = useAsState (mkHsValueMap state_ty)
205 -- All but the last argument are inports
206 inports = map (useAsPort . mkHsValueMap)(init arg_tys)
207 hsargs = inports ++ [state]
208 hsres = case splitTupleType res_ty of
209 -- Result type must be a two tuple (state, ports)
210 Just [outstate_ty, outport_ty] -> if Type.coreEqType state_ty outstate_ty
212 Tuple [state, useAsPort (mkHsValueMap outport_ty)]
214 error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty)
215 otherwise -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports."
217 -- | Adds signal names to the given FlatFunction
223 nameFlatFunction hsfunc fdata =
224 let func = flatFunc fdata in
226 -- Skip (builtin) functions without a FlatFunction
227 Nothing -> do return ()
228 -- Name the signals in all other functions
230 let s = flat_sigs flatfunc in
231 let s' = map nameSignal s in
232 let flatfunc' = flatfunc { flat_sigs = s' } in
233 setFlatFunc hsfunc flatfunc'
235 nameSignal :: (SignalId, SignalInfo) -> (SignalId, SignalInfo)
236 nameSignal (id, info) =
237 let hints = nameHints info in
238 let parts = ("sig" : hints) ++ [show id] in
239 let name = concat $ List.intersperse "_" parts in
240 (id, info {sigName = Just name})
242 -- | Splits a tuple type into a list of element types, or Nothing if the type
243 -- is not a tuple type.
245 Type -- ^ The type to split
246 -> Maybe [Type] -- ^ The tuples element types
249 case Type.splitTyConApp_maybe ty of
250 Just (tycon, args) -> if TyCon.isTupleTyCon tycon
257 -- | A consise representation of a (set of) ports on a builtin function
258 type PortMap = HsValueMap (String, AST.TypeMark)
259 -- | A consise representation of a builtin function
260 data BuiltIn = BuiltIn String [PortMap] PortMap
262 -- | Map a port specification of a builtin function to a VHDL Signal to put in
264 toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
265 toVHDLSignalMap = fmap (\(name, ty) -> Just (VHDL.mkVHDLId name, ty))
267 -- | Translate a concise representation of a builtin function to something
268 -- that can be put into FuncMap directly.
269 addBuiltIn :: BuiltIn -> VHDLState ()
270 addBuiltIn (BuiltIn name args res) = do
272 setEntity hsfunc entity
274 hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
275 entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
279 BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
280 BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
281 BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
282 BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
285 -- vim: set ts=8 sw=2 sts=2 expandtab: