1 module Pretty (prettyShow) where
3 import qualified Data.Map as Map
4 import qualified CoreSyn
5 import qualified Module
6 import qualified HscTypes
7 import Text.PrettyPrint.HughesPJClass
8 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
10 import qualified ForSyDe.Backend.Ppr
11 import qualified ForSyDe.Backend.VHDL.AST as AST
15 import TranslatorTypes
18 instance Pretty HsFunction where
19 pPrint (HsFunction name args res) =
20 text name <> char ' ' <> parens (hsep $ punctuate comma args') <> text " -> " <> res'
22 args' = map pPrint args
25 instance Pretty x => Pretty (HsValueMap x) where
26 pPrint (Tuple maps) = parens (hsep $ punctuate comma (map pPrint maps))
27 pPrint (Single s) = pPrint s
29 instance Pretty HsValueUse where
30 pPrint Port = char 'P'
31 pPrint (State n) = char 'C' <> int n
32 pPrint (HighOrder _ _) = text "Higher Order"
34 instance Pretty id => Pretty (FlatFunction' id) where
35 pPrint (FlatFunction args res apps conds sigs) =
36 (text "Args: ") $$ nest 10 (pPrint args)
37 $+$ (text "Result: ") $$ nest 10 (pPrint res)
38 $+$ (text "Apps: ") $$ nest 10 (vcat (map pPrint apps))
39 $+$ (text "Conds: ") $$ nest 10 (pPrint conds)
40 $+$ text "Signals: " $$ nest 10 (pPrint sigs)
42 instance Pretty id => Pretty (FApp id) where
43 pPrint (FApp func args res) =
44 pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res
46 instance Pretty id => Pretty (CondDef id) where
47 pPrint _ = text "TODO"
49 instance Pretty SignalInfo where
50 pPrint (SignalInfo Nothing ty) = empty
51 pPrint (SignalInfo (Just name) ty) = text ":" <> text name
53 instance Pretty VHDLSession where
54 pPrint (VHDLSession mod nameCount funcs) =
55 text "Module: " $$ nest 15 (text modname)
56 $+$ text "NameCount: " $$ nest 15 (int nameCount)
57 $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
59 ppfunc (hsfunc, fdata) =
60 pPrint hsfunc $+$ nest 5 (pPrint fdata)
61 modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
63 instance Pretty FuncData where
64 pPrint (FuncData flatfunc entity arch) =
65 text "Flattened: " $$ nest 15 (ppffunc flatfunc)
66 $+$ text "Entity" $$ nest 15 (ppent entity)
69 ppffunc (Just f) = pPrint f
70 ppffunc Nothing = text "Nothing"
71 ppent (Just e) = pPrint e
72 ppent Nothing = text "Nothing"
73 pparch Nothing = text "VHDL architecture not present"
74 pparch (Just _) = text "VHDL architecture present"
76 instance Pretty Entity where
77 pPrint (Entity id args res decl) =
78 text "Entity id: " $$ nest 10 (pPrint id)
79 $+$ text "Args: " $$ nest 10 (pPrint args)
80 $+$ text "Result: " $$ nest 10 (pPrint res)
83 ppdecl Nothing = text "VHDL entity not present"
84 ppdecl (Just _) = text "VHDL entity present"
86 instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
87 pPrint (CoreSyn.NonRec b expr) =
88 text "NonRec: " $$ nest 10 (prettyBind (b, expr))
89 pPrint (CoreSyn.Rec binds) =
90 text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
92 instance Pretty AST.VHDLId where
93 pPrint id = ForSyDe.Backend.Ppr.ppr id
95 prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
96 prettyBind (b, expr) =
97 text b' <> text " = " <> text expr'
100 expr' = showSDoc $ ppr expr