4 {-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-}
7 import qualified Prelude as P
11 \section{Polymorphic, Higher-Order CPU}
12 \subsection{Introduction}
15 \frametitle{Small Use Case}
17 \item Small Polymorphic, Higher-Order CPU
18 \item Each function is turned into a hardware component
19 \item Use of state will be simple
27 import {-"{\color<2>[rgb]{1,0,0}"-}CLasH.HardwareTypes{-"}"-}
28 import {-"{\color<3>[rgb]{1,0,0}"-}CLasH.Translator.Annotations{-"}"-}
32 \subsection{Type Definitions}
35 First we define some ALU types:
37 type Op s a = a -> {-"{\color<2>[rgb]{1,0,0}"-}Vector s a{-"}"-} -> a
40 And some Register types:
42 type RegBank s a = {-"{\color<2>[rgb]{1,0,0}"-}Vector (s :+: D1){-"}"-} a
43 type RegState s a = State (RegBank s a)
45 And a simple Word type:
47 type Word = {-"{\color<3>[rgb]{1,0,0}"-}SizedInt D12{-"}"-}
50 \subsection{Frameworks for Operations}
53 We make a primitive operation:
55 primOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
56 primOp f a b = a `f` a
58 We make a vector operation:
60 vectOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
61 vectOp f a b = {-"{\color<2>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
64 \subsection{Polymorphic, Higher-Order ALU}
67 We define a polymorphic ALU:
72 Opcode -> a -> Vector s a -> a
73 alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-} a b = op1 a b
74 alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b
77 \subsection{Register bank}
80 Make a simple register bank:
83 CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
84 (RegState s a) -> a -> {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} ->
85 {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} -> Bit -> ((RegState s a), a )
87 registerBank (State mem) data_in rdaddr wraddr wrenable =
88 ((State mem'), data_out)
91 mem' {-"{\color<3>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-} = mem
92 {-"{\color<3>[rgb]{1,0,0}"-}| otherwise{-"}"-} = replace mem wraddr data_in
95 \subsection{Simple CPU: ALU \& Register Bank}
98 Combining ALU and register bank:
100 {-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-}
102 (Opcode, Word, Vector D4 Word,
104 RangedWord D9, Bit) ->
106 (RegState D9 Word, Word)
108 actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
110 alu_out = alu simpleOp vectorOp opc ram_out b
111 (ram',ram_out) = registerBank ram a rdaddr wraddr wren
112 simpleOp = primOp (+)
113 vectorOp = vectOp (+)