4 import qualified Control.Monad as Monad
5 import qualified Data.Map as Map
7 import qualified Data.Either as Either
12 import qualified ForSyDe.Backend.VHDL.AST as AST
18 import qualified IdInfo
27 -----------------------------------------------------------------------------
28 -- Functions to generate VHDL for builtin functions
29 -----------------------------------------------------------------------------
31 -- | A function to wrap a builder-like function that expects its arguments to
34 (dst -> func -> [AST.Expr] -> res)
35 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
36 genExprArgs wrap dst func args = wrap dst func args'
37 where args' = map (either (varToVHDLExpr.exprToVar) id) args
39 -- | A function to wrap a builder-like function that expects its arguments to
42 (dst -> func -> [Var.Var] -> res)
43 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
44 genVarArgs wrap dst func args = wrap dst func args'
46 args' = map exprToVar exprargs
47 -- Check (rather crudely) that all arguments are CoreExprs
48 (exprargs, []) = Either.partitionEithers args
50 -- | A function to wrap a builder-like function that produces an expression
51 -- and expects it to be assigned to the destination.
53 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession AST.Expr)
54 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession [AST.ConcSm])
55 genExprRes wrap dst func args = do
56 expr <- wrap dst func args
57 return $ [mkUncondAssign dst expr]
59 -- | Generate a binary operator application. The first argument should be a
60 -- constructor from the AST.Expr type, e.g. AST.And.
61 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
62 genOperator2 op = genExprArgs $ genExprRes (genOperator2' op)
63 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
64 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
66 -- | Generate a unary operator application
67 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
68 genOperator1 op = genExprArgs $ genExprRes (genOperator1' op)
69 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
70 genOperator1' op _ f [arg] = return $ op arg
72 -- | Generate a function call from the destination binder, function name and a
73 -- list of expressions (its arguments)
74 genFCall :: BuiltinBuilder
75 genFCall = genExprArgs $ genExprRes genFCall'
76 genFCall' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
77 genFCall' (Left res) f args = do
78 let fname = varToString f
79 let el_ty = (tfvec_elem . Var.varType) res
80 id <- vectorFunId el_ty fname
81 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
82 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
83 genFCall' (Right name) _ _ = error $ "Cannot generate builtin function call assigned to a VHDLName: " ++ show name
85 -- | Generate a generate statement for the builtin function "map"
86 genMap :: BuiltinBuilder
87 genMap = genVarArgs genMap'
88 genMap' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
89 genMap' (Left res) f [mapped_f, arg] =
91 -- Setup the generate scheme
92 len = (tfvec_len . Var.varType) res
93 -- TODO: Use something better than varToString
94 label = mkVHDLExtId ("mapVector" ++ (varToString res))
95 n_id = mkVHDLBasicId "n"
96 n_expr = idToVHDLExpr n_id
97 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
98 genScheme = AST.ForGn n_id range
100 -- Create the content of the generate statement: Applying the mapped_f to
101 -- each of the elements in arg, storing to each element in res
102 resname = mkIndexedName (varToVHDLName res) n_expr
103 argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
105 app_concsms <- genApplication (Right resname) mapped_f [Right argexpr]
106 -- Return the generate statement
107 return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
109 genMap' (Right name) _ _ = error $ "Cannot generate map function call assigned to a VHDLName: " ++ show name
111 genZipWith :: BuiltinBuilder
112 genZipWith = genVarArgs genZipWith'
113 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
114 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] =
116 -- Setup the generate scheme
117 len = (tfvec_len . Var.varType) res
118 -- TODO: Use something better than varToString
119 label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
120 n_id = mkVHDLBasicId "n"
121 n_expr = idToVHDLExpr n_id
122 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
123 genScheme = AST.ForGn n_id range
125 -- Create the content of the generate statement: Applying the zipped_f to
126 -- each of the elements in arg1 and arg2, storing to each element in res
127 resname = mkIndexedName (varToVHDLName res) n_expr
128 argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
129 argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
131 app_concsms <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
132 -- Return the generate functions
133 return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
135 genFoldl :: BuiltinBuilder
136 genFoldl = genVarArgs genFoldl'
137 genFoldl' resVal f [folded_f, startVal, inVec] = do
138 signatures <- getA vsSignatures
139 let entity = Maybe.fromMaybe
140 (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!")
141 (Map.lookup folded_f signatures)
142 let (vec, _) = splitAppTy (Var.varType inVec)
143 let vecty = Type.mkAppTy vec (Var.varType startVal)
144 vecType <- vhdl_ty vecty
145 -- Setup the generate scheme
146 let len = (tfvec_len . Var.varType) inVec
147 let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
148 let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
149 let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
150 let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range
151 -- Make the intermediate vector
152 let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing
153 -- Get the entity name and port names
154 let entity_id = ent_id entity
155 let argports = map (Monad.liftM fst) (ent_args entity)
156 let resport = (Monad.liftM fst) (ent_res entity)
157 -- Return the generate functions
158 let genSm = AST.GenerateSm genlabel genScheme []
159 [ AST.CSGSm (genFirstCell (entity_id, argports, resport)
160 [startVal, inVec, resVal])
161 , AST.CSGSm (genOtherCell (entity_id, argports, resport)
162 [startVal, inVec, resVal])
163 , AST.CSGSm (genLastCell (entity_id, argports, resport)
164 [startVal, inVec, resVal])
166 return $ [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]]
168 genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
170 cellLabel = mkVHDLExtId "firstcell"
171 cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0"))
172 tmpId = mkVHDLExtId "tmp"
173 nPar = AST.unsafeVHDLBasicId "n"
175 inport1 = mkAssocElem (argports!!0) (varToString startVal)
176 inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
177 outport = mkAssocElemIndexed resport tmpId nPar
178 portassigns = Maybe.catMaybes [inport1,inport2,outport]
179 -- Generate the portmap
180 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
181 compins = mkComponentInst mapLabel entity_id portassigns
182 -- Return the generate functions
183 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
184 genOtherCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
186 len = (tfvec_len . Var.varType) inVec
187 cellLabel = mkVHDLExtId "othercell"
188 cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0"))
189 ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1)))
190 tmpId = mkVHDLExtId "tmp"
191 nPar = AST.unsafeVHDLBasicId "n"
193 inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
194 inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
195 outport = mkAssocElemIndexed resport tmpId nPar
196 portassigns = Maybe.catMaybes [inport1,inport2,outport]
197 -- Generate the portmap
198 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
199 compins = mkComponentInst mapLabel entity_id portassigns
200 -- Return the generate functions
201 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
202 genLastCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
204 len = (tfvec_len . Var.varType) inVec
205 cellLabel = mkVHDLExtId "lastCell"
206 cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1)))
207 tmpId = mkVHDLExtId "tmp"
208 nPar = AST.unsafeVHDLBasicId "n"
210 inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
211 inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
212 outport = mkAssocElemIndexed resport tmpId nPar
213 portassigns = Maybe.catMaybes [inport1,inport2,outport]
214 -- Generate the portmap
215 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
216 compins = mkComponentInst mapLabel entity_id portassigns
217 -- Generate the output assignment
218 assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName
219 (AST.NSimple tmpId) [AST.PrimLit $ show (len-1)])))
220 -- Return the generate functions
221 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign]
223 -----------------------------------------------------------------------------
224 -- Function to generate VHDL for applications
225 -----------------------------------------------------------------------------
227 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
228 -> CoreSyn.CoreBndr -- ^ The function to apply
229 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
230 -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements
231 genApplication dst f args =
232 case Var.globalIdVarDetails f of
233 IdInfo.DataConWorkId dc -> case dst of
234 -- It's a datacon. Create a record from its arguments.
236 -- We have the bndr, so we can get at the type
237 labels <- getFieldLabels (Var.varType bndr)
238 return $ zipWith mkassign labels $ map (either exprToVHDLExpr id) args
240 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
242 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
243 mkUncondAssign (Right sel_name) arg
244 Right _ -> error $ "Generate.genApplication Can't generate dataconstructor application without an original binder"
245 IdInfo.VanillaGlobal -> do
246 -- It's a global value imported from elsewhere. These can be builtin
247 -- functions. Look up the function name in the name table and execute
248 -- the associated builder if there is any and the argument count matches
249 -- (this should always be the case if it typechecks, but just to be
251 case (Map.lookup (varToString f) globalNameTable) of
252 Just (arg_count, builder) ->
253 if length args == arg_count then
256 error $ "Generate.genApplication Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
257 Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
258 IdInfo.NotGlobalId -> do
259 signatures <- getA vsSignatures
260 -- This is a local id, so it should be a function whose definition we
261 -- have and which can be turned into a component instantiation.
263 signature = Maybe.fromMaybe
264 (error $ "Using function '" ++ (varToString f) ++ "' without signature? This should not happen!")
265 (Map.lookup f signatures)
266 entity_id = ent_id signature
267 -- TODO: Using show here isn't really pretty, but we'll need some
268 -- unique-ish value...
269 label = "comp_ins_" ++ (either show show) dst
270 portmaps = mkAssocElems (map (either exprToVHDLExpr id) args) ((either varToVHDLName id) dst) signature
272 return [mkComponentInst label entity_id portmaps]
273 details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
275 -----------------------------------------------------------------------------
276 -- Functions to generate functions dealing with vectors.
277 -----------------------------------------------------------------------------
279 -- Returns the VHDLId of the vector function with the given name for the given
280 -- element type. Generates -- this function if needed.
281 vectorFunId :: Type.Type -> String -> VHDLSession AST.VHDLId
282 vectorFunId el_ty fname = do
283 elemTM <- vhdl_ty el_ty
284 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
285 -- the VHDLState or something.
286 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
287 typefuns <- getA vsTypeFuns
288 case Map.lookup (OrdType el_ty, fname) typefuns of
289 -- Function already generated, just return it
290 Just (id, _) -> return id
291 -- Function not generated yet, generate it
293 let functions = genUnconsVectorFuns elemTM vectorTM
294 case lookup fname functions of
296 modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, body)
298 Nothing -> error $ "I don't know how to generate vector function " ++ fname
300 function_id = mkVHDLExtId fname
302 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
303 -> AST.TypeMark -- ^ type of the vector
304 -> [(String, AST.SubProgBody)]
305 genUnconsVectorFuns elemTM vectorTM =
306 [ (exId, AST.SubProgBody exSpec [] [exExpr])
307 , (replaceId, AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet])
308 , (headId, AST.SubProgBody headSpec [] [headExpr])
309 , (lastId, AST.SubProgBody lastSpec [] [lastExpr])
310 , (initId, AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet])
311 , (tailId, AST.SubProgBody tailSpec [AST.SPVD tailVar] [tailExpr, tailRet])
312 , (takeId, AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet])
313 , (dropId, AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet])
314 , (plusgtId, AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet])
315 , (emptyId, AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr])
316 , (singletonId, AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet])
317 , (copyId, AST.SubProgBody copySpec [AST.SPVD copyVar] [copyExpr])
320 ixPar = AST.unsafeVHDLBasicId "ix"
321 vecPar = AST.unsafeVHDLBasicId "vec"
322 nPar = AST.unsafeVHDLBasicId "n"
323 iId = AST.unsafeVHDLBasicId "i"
325 aPar = AST.unsafeVHDLBasicId "a"
326 resId = AST.unsafeVHDLBasicId "res"
327 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
328 AST.IfaceVarDec ixPar naturalTM] elemTM
329 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
330 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
332 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
333 , AST.IfaceVarDec iPar naturalTM
334 , AST.IfaceVarDec aPar elemTM
336 -- variable res : fsvec_x (0 to vec'length-1);
339 (AST.SubtypeIn vectorTM
340 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
341 [AST.ToRange (AST.PrimLit "0")
342 (AST.PrimName (AST.NAttribute $
343 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
344 (AST.PrimLit "1")) ]))
346 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
347 replaceExpr = AST.NSimple resId AST.:=
348 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
349 AST.PrimName (AST.NSimple aPar) AST.:&:
350 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
351 ((AST.PrimName (AST.NAttribute $
352 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
353 AST.:-: AST.PrimLit "1"))
354 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
355 vecSlice init last = AST.PrimName (AST.NSlice
358 (AST.ToRange init last)))
359 headSpec = AST.Function (mkVHDLExtId headId) [AST.IfaceVarDec vecPar vectorTM] elemTM
361 headExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
362 (AST.NSimple vecPar) [AST.PrimLit "0"])))
363 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
364 -- return vec(vec'length-1);
365 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
367 [AST.PrimName (AST.NAttribute $
368 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
369 AST.:-: AST.PrimLit "1"])))
370 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
371 -- variable res : fsvec_x (0 to vec'length-2);
374 (AST.SubtypeIn vectorTM
375 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
376 [AST.ToRange (AST.PrimLit "0")
377 (AST.PrimName (AST.NAttribute $
378 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
379 (AST.PrimLit "2")) ]))
381 -- resAST.:= vec(0 to vec'length-2)
382 initExpr = AST.NSimple resId AST.:= (vecSlice
384 (AST.PrimName (AST.NAttribute $
385 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
386 AST.:-: AST.PrimLit "2"))
387 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
388 tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
389 -- variable res : fsvec_x (0 to vec'length-2);
392 (AST.SubtypeIn vectorTM
393 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
394 [AST.ToRange (AST.PrimLit "0")
395 (AST.PrimName (AST.NAttribute $
396 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
397 (AST.PrimLit "2")) ]))
399 -- res AST.:= vec(1 to vec'length-1)
400 tailExpr = AST.NSimple resId AST.:= (vecSlice
402 (AST.PrimName (AST.NAttribute $
403 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
404 AST.:-: AST.PrimLit "1"))
405 tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
406 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
407 AST.IfaceVarDec vecPar vectorTM ] vectorTM
408 -- variable res : fsvec_x (0 to n-1);
411 (AST.SubtypeIn vectorTM
412 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
413 [AST.ToRange (AST.PrimLit "0")
414 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
415 (AST.PrimLit "1")) ]))
417 -- res AST.:= vec(0 to n-1)
418 takeExpr = AST.NSimple resId AST.:=
419 (vecSlice (AST.PrimLit "1")
420 (AST.PrimName (AST.NSimple $ nPar) AST.:-: AST.PrimLit "1"))
421 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
422 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
423 AST.IfaceVarDec vecPar vectorTM ] vectorTM
424 -- variable res : fsvec_x (0 to vec'length-n-1);
427 (AST.SubtypeIn vectorTM
428 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
429 [AST.ToRange (AST.PrimLit "0")
430 (AST.PrimName (AST.NAttribute $
431 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
432 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
434 -- res AST.:= vec(n to vec'length-1)
435 dropExpr = AST.NSimple resId AST.:= (vecSlice
436 (AST.PrimName $ AST.NSimple nPar)
437 (AST.PrimName (AST.NAttribute $
438 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
439 AST.:-: AST.PrimLit "1"))
440 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
441 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
442 AST.IfaceVarDec vecPar vectorTM] vectorTM
443 -- variable res : fsvec_x (0 to vec'length);
446 (AST.SubtypeIn vectorTM
447 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
448 [AST.ToRange (AST.PrimLit "0")
449 (AST.PrimName (AST.NAttribute $
450 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
452 plusgtExpr = AST.NSimple resId AST.:=
453 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
454 (AST.PrimName $ AST.NSimple vecPar))
455 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
456 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
459 (AST.SubtypeIn vectorTM Nothing)
460 (Just $ AST.PrimLit "\"\"")
461 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
462 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
464 -- variable res : fsvec_x (0 to 0) := (others => a);
467 (AST.SubtypeIn vectorTM
468 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
469 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
470 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
471 (AST.PrimName $ AST.NSimple aPar)])
472 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
473 copySpec = AST.Function (mkVHDLExtId copyId) [AST.IfaceVarDec nPar naturalTM,
474 AST.IfaceVarDec aPar elemTM ] vectorTM
475 -- variable res : fsvec_x (0 to n-1) := (others => a);
478 (AST.SubtypeIn vectorTM
479 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
480 [AST.ToRange (AST.PrimLit "0")
481 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
482 (AST.PrimLit "1")) ]))
483 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
484 (AST.PrimName $ AST.NSimple aPar)])
486 copyExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
488 -----------------------------------------------------------------------------
489 -- A table of builtin functions
490 -----------------------------------------------------------------------------
492 -- | The builtin functions we support. Maps a name to an argument count and a
494 globalNameTable :: NameTable
495 globalNameTable = Map.fromList
496 [ (exId , (2, genFCall ) )
497 , (replaceId , (3, genFCall ) )
498 , (headId , (1, genFCall ) )
499 , (lastId , (1, genFCall ) )
500 , (tailId , (1, genFCall ) )
501 , (initId , (1, genFCall ) )
502 , (takeId , (2, genFCall ) )
503 , (dropId , (2, genFCall ) )
504 , (plusgtId , (2, genFCall ) )
505 , (mapId , (2, genMap ) )
506 , (zipWithId , (3, genZipWith ) )
507 --, (foldlId , (3, genFoldl ) )
508 , (emptyId , (0, genFCall ) )
509 , (singletonId , (1, genFCall ) )
510 , (copyId , (2, genFCall ) )
511 , (hwxorId , (2, genOperator2 AST.Xor ) )
512 , (hwandId , (2, genOperator2 AST.And ) )
513 , (hworId , (2, genOperator2 AST.Or ) )
514 , (hwnotId , (1, genOperator1 AST.Not ) )