1 {-# LANGUAGE PackageImports #-}
6 import qualified Control.Monad as Monad
7 import qualified Data.Map as Map
9 import qualified Data.Either as Either
10 import qualified Control.Monad.Trans.State as State
11 import qualified "transformers" Control.Monad.Identity as Identity
13 import Data.Accessor.MonadState as MonadState
17 import qualified ForSyDe.Backend.VHDL.AST as AST
23 import qualified IdInfo
24 import qualified Literal
26 import qualified TyCon
35 -----------------------------------------------------------------------------
36 -- Functions to generate VHDL for builtin functions
37 -----------------------------------------------------------------------------
39 -- | A function to wrap a builder-like function that expects its arguments to
41 genExprArgs wrap dst func args = do
42 args' <- eitherCoreOrExprArgs args
45 eitherCoreOrExprArgs :: [Either CoreSyn.CoreExpr AST.Expr] -> VHDLSession [AST.Expr]
46 eitherCoreOrExprArgs args = mapM (Either.either ((MonadState.lift vsType) . varToVHDLExpr . exprToVar) return) args
48 -- | A function to wrap a builder-like function that expects its arguments to
51 (dst -> func -> [Var.Var] -> res)
52 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
53 genVarArgs wrap dst func args = wrap dst func args'
55 args' = map exprToVar exprargs
56 -- Check (rather crudely) that all arguments are CoreExprs
57 (exprargs, []) = Either.partitionEithers args
59 -- | A function to wrap a builder-like function that expects its arguments to
62 (dst -> func -> [Literal.Literal] -> res)
63 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
64 genLitArgs wrap dst func args = wrap dst func args'
66 args' = map exprToLit litargs
67 -- FIXME: Check if we were passed an CoreSyn.App
68 litargs = concat (map getLiterals exprargs)
69 (exprargs, []) = Either.partitionEithers args
71 -- | A function to wrap a builder-like function that produces an expression
72 -- and expects it to be assigned to the destination.
74 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession AST.Expr)
75 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession [AST.ConcSm])
76 genExprRes wrap dst func args = do
77 expr <- wrap dst func args
78 return $ [mkUncondAssign dst expr]
80 -- | Generate a binary operator application. The first argument should be a
81 -- constructor from the AST.Expr type, e.g. AST.And.
82 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
83 genOperator2 op = genExprArgs $ genExprRes (genOperator2' op)
84 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
85 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
87 -- | Generate a unary operator application
88 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
89 genOperator1 op = genExprArgs $ genExprRes (genOperator1' op)
90 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
91 genOperator1' op _ f [arg] = return $ op arg
93 -- | Generate a unary operator application
94 genNegation :: BuiltinBuilder
95 genNegation = genVarArgs $ genExprRes genNegation'
96 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession AST.Expr
97 genNegation' _ f [arg] = do
98 arg1 <- MonadState.lift vsType $ varToVHDLExpr arg
99 let ty = Var.varType arg
100 let (tycon, args) = Type.splitTyConApp ty
101 let name = Name.getOccString (TyCon.tyConName tycon)
103 "SizedInt" -> return $ AST.Neg arg1
104 otherwise -> error $ "\nGenerate.genNegation': Negation allowed for type: " ++ show name
106 -- | Generate a function call from the destination binder, function name and a
107 -- list of expressions (its arguments)
108 genFCall :: Bool -> BuiltinBuilder
109 genFCall switch = genExprArgs $ genExprRes (genFCall' switch)
110 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
111 genFCall' switch (Left res) f args = do
112 let fname = varToString f
113 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
114 id <- MonadState.lift vsType $ vectorFunId el_ty fname
115 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
116 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
117 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
119 genFromSizedWord :: BuiltinBuilder
120 genFromSizedWord = genExprArgs $ genExprRes genFromSizedWord'
121 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
122 genFromSizedWord' (Left res) f args = do
123 let fname = varToString f
124 return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
125 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
126 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
128 -- FIXME: I'm calling genLitArgs which is very specific function,
129 -- which needs to be fixed as well
130 genFromInteger :: BuiltinBuilder
131 genFromInteger = genLitArgs $ genExprRes genFromInteger'
132 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> VHDLSession AST.Expr
133 genFromInteger' (Left res) f lits = do {
134 ; let { ty = Var.varType res
135 ; (tycon, args) = Type.splitTyConApp ty
136 ; name = Name.getOccString (TyCon.tyConName tycon)
138 ; len <- case name of
139 "SizedInt" -> MonadState.lift vsType $ tfp_to_int (sized_int_len_ty ty)
140 "SizedWord" -> MonadState.lift vsType $ tfp_to_int (sized_word_len_ty ty)
141 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId
142 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
143 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
146 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
149 -- | Generate a generate statement for the builtin function "map"
150 genMap :: BuiltinBuilder
151 genMap (Left res) f [Left mapped_f, Left (Var arg)] = do {
152 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
153 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
154 -- we must index it (which we couldn't if it was a VHDL Expr, since only
155 -- VHDLNames can be indexed).
156 -- Setup the generate scheme
157 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
158 -- TODO: Use something better than varToString
159 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
160 ; n_id = mkVHDLBasicId "n"
161 ; n_expr = idToVHDLExpr n_id
162 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
163 ; genScheme = AST.ForGn n_id range
164 -- Create the content of the generate statement: Applying the mapped_f to
165 -- each of the elements in arg, storing to each element in res
166 ; resname = mkIndexedName (varToVHDLName res) n_expr
167 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
168 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
169 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
171 ; app_concsms <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
172 -- Return the generate statement
173 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
176 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
178 genZipWith :: BuiltinBuilder
179 genZipWith = genVarArgs genZipWith'
180 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
181 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do {
182 -- Setup the generate scheme
183 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
184 -- TODO: Use something better than varToString
185 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
186 ; n_id = mkVHDLBasicId "n"
187 ; n_expr = idToVHDLExpr n_id
188 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
189 ; genScheme = AST.ForGn n_id range
190 -- Create the content of the generate statement: Applying the zipped_f to
191 -- each of the elements in arg1 and arg2, storing to each element in res
192 ; resname = mkIndexedName (varToVHDLName res) n_expr
193 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
194 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
196 ; app_concsms <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
197 -- Return the generate functions
198 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
201 genFoldl :: BuiltinBuilder
202 genFoldl = genFold True
204 genFoldr :: BuiltinBuilder
205 genFoldr = genFold False
207 genFold :: Bool -> BuiltinBuilder
208 genFold left = genVarArgs (genFold' left)
210 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
211 genFold' left res f args@[folded_f , start ,vec]= do
212 len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty (Var.varType vec))
213 genFold'' len left res f args
215 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
216 -- Special case for an empty input vector, just assign start to res
217 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
218 arg <- MonadState.lift vsType $ varToVHDLExpr start
219 return [mkUncondAssign (Left res) arg]
221 genFold'' len left (Left res) f [folded_f, start, vec] = do
223 --len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
224 -- An expression for len-1
225 let len_min_expr = (AST.PrimLit $ show (len-1))
226 -- evec is (TFVec n), so it still needs an element type
227 let (nvec, _) = splitAppTy (Var.varType vec)
228 -- Put the type of the start value in nvec, this will be the type of our
230 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
231 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
232 tmp_vhdl_ty <- MonadState.lift vsType $ vhdl_ty error_msg tmp_ty
233 -- Setup the generate scheme
234 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
235 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString start))
236 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
237 else AST.DownRange len_min_expr (AST.PrimLit "0")
238 let gen_scheme = AST.ForGn n_id gen_range
239 -- Make the intermediate vector
240 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
241 -- Create the generate statement
242 cells <- sequence [genFirstCell, genOtherCell]
243 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
244 -- Assign tmp[len-1] or tmp[0] to res
245 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
246 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
247 (mkIndexedName tmp_name (AST.PrimLit "0")))
248 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
249 return [AST.CSBSm block]
251 -- An id for the counter
252 n_id = mkVHDLBasicId "n"
253 n_cur = idToVHDLExpr n_id
254 -- An expression for previous n
255 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
256 else (n_cur AST.:+: (AST.PrimLit "1"))
257 -- An id for the tmp result vector
258 tmp_id = mkVHDLBasicId "tmp"
259 tmp_name = AST.NSimple tmp_id
260 -- Generate parts of the fold
261 genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm
263 len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
264 let cond_label = mkVHDLExtId "firstcell"
265 -- if n == 0 or n == len-1
266 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
267 else (AST.PrimLit $ show (len-1)))
268 -- Output to tmp[current n]
269 let resname = mkIndexedName tmp_name n_cur
271 argexpr1 <- MonadState.lift vsType $ varToVHDLExpr start
272 -- Input from vec[current n]
273 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
274 app_concsms <- genApplication (Right resname) folded_f ( if left then
275 [Right argexpr1, Right argexpr2]
277 [Right argexpr2, Right argexpr1]
279 -- Return the conditional generate part
280 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
283 len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
284 let cond_label = mkVHDLExtId "othercell"
285 -- if n > 0 or n < len-1
286 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
287 else (AST.PrimLit $ show (len-1)))
288 -- Output to tmp[current n]
289 let resname = mkIndexedName tmp_name n_cur
290 -- Input from tmp[previous n]
291 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
292 -- Input from vec[current n]
293 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
294 app_concsms <- genApplication (Right resname) folded_f ( if left then
295 [Right argexpr1, Right argexpr2]
297 [Right argexpr2, Right argexpr1]
299 -- Return the conditional generate part
300 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
302 -- | Generate a generate statement for the builtin function "zip"
303 genZip :: BuiltinBuilder
304 genZip = genVarArgs genZip'
305 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
306 genZip' (Left res) f args@[arg1, arg2] = do {
307 -- Setup the generate scheme
308 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
309 -- TODO: Use something better than varToString
310 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
311 ; n_id = mkVHDLBasicId "n"
312 ; n_expr = idToVHDLExpr n_id
313 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
314 ; genScheme = AST.ForGn n_id range
315 ; resname' = mkIndexedName (varToVHDLName res) n_expr
316 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
317 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
319 ; labels <- MonadState.lift vsType $ getFieldLabels (tfvec_elem (Var.varType res))
320 ; let { resnameA = mkSelectedName resname' (labels!!0)
321 ; resnameB = mkSelectedName resname' (labels!!1)
322 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
323 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
325 -- Return the generate functions
326 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
329 -- | Generate a generate statement for the builtin function "unzip"
330 genUnzip :: BuiltinBuilder
331 genUnzip = genVarArgs genUnzip'
332 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
333 genUnzip' (Left res) f args@[arg] = do {
334 -- Setup the generate scheme
335 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
336 -- TODO: Use something better than varToString
337 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
338 ; n_id = mkVHDLBasicId "n"
339 ; n_expr = idToVHDLExpr n_id
340 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
341 ; genScheme = AST.ForGn n_id range
342 ; resname' = varToVHDLName res
343 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
345 ; reslabels <- MonadState.lift vsType $ getFieldLabels (Var.varType res)
346 ; arglabels <- MonadState.lift vsType $ getFieldLabels (tfvec_elem (Var.varType arg))
347 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
348 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
349 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
350 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
351 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
352 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
354 -- Return the generate functions
355 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
358 genCopy :: BuiltinBuilder
359 genCopy = genVarArgs genCopy'
360 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
361 genCopy' (Left res) f args@[arg] =
363 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
364 (AST.PrimName $ (varToVHDLName arg))]
365 out_assign = mkUncondAssign (Left res) resExpr
369 genConcat :: BuiltinBuilder
370 genConcat = genVarArgs genConcat'
371 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
372 genConcat' (Left res) f args@[arg] = do {
373 -- Setup the generate scheme
374 ; len1 <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
375 ; let (_, nvec) = splitAppTy (Var.varType arg)
376 ; len2 <- MonadState.lift vsType $ tfp_to_int $ tfvec_len_ty nvec
377 -- TODO: Use something better than varToString
378 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
379 ; n_id = mkVHDLBasicId "n"
380 ; n_expr = idToVHDLExpr n_id
381 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
382 ; genScheme = AST.ForGn n_id range
383 -- Create the content of the generate statement: Applying the mapped_f to
384 -- each of the elements in arg, storing to each element in res
385 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
386 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
387 ; resname = vecSlice fromRange toRange
388 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
389 ; out_assign = mkUncondAssign (Right resname) argexpr
391 -- Return the generate statement
392 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
395 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
396 (AST.ToRange init last))
398 genIteraten :: BuiltinBuilder
399 genIteraten dst f args = genIterate dst f (tail args)
401 genIterate :: BuiltinBuilder
402 genIterate = genIterateOrGenerate True
404 genGeneraten :: BuiltinBuilder
405 genGeneraten dst f args = genGenerate dst f (tail args)
407 genGenerate :: BuiltinBuilder
408 genGenerate = genIterateOrGenerate False
410 genIterateOrGenerate :: Bool -> BuiltinBuilder
411 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
413 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
414 genIterateOrGenerate' iter (Left res) f args = do
415 len <- MonadState.lift vsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
416 genIterateOrGenerate'' len iter (Left res) f args
418 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
419 -- Special case for an empty input vector, just assign start to res
420 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return [mkUncondAssign (Left res) (AST.PrimLit "\"\"")]
422 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
424 -- len <- MonadState.lift vsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
425 -- An expression for len-1
426 let len_min_expr = (AST.PrimLit $ show (len-1))
427 -- -- evec is (TFVec n), so it still needs an element type
428 -- let (nvec, _) = splitAppTy (Var.varType vec)
429 -- -- Put the type of the start value in nvec, this will be the type of our
430 -- -- temporary vector
431 let tmp_ty = Var.varType res
432 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
433 tmp_vhdl_ty <- MonadState.lift vsType $ vhdl_ty error_msg tmp_ty
434 -- Setup the generate scheme
435 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
436 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
437 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
438 let gen_scheme = AST.ForGn n_id gen_range
439 -- Make the intermediate vector
440 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
441 -- Create the generate statement
442 cells <- sequence [genFirstCell, genOtherCell]
443 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
444 -- Assign tmp[len-1] or tmp[0] to res
445 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
446 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
447 return [AST.CSBSm block]
449 -- An id for the counter
450 n_id = mkVHDLBasicId "n"
451 n_cur = idToVHDLExpr n_id
452 -- An expression for previous n
453 n_prev = n_cur AST.:-: (AST.PrimLit "1")
454 -- An id for the tmp result vector
455 tmp_id = mkVHDLBasicId "tmp"
456 tmp_name = AST.NSimple tmp_id
457 -- Generate parts of the fold
458 genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm
460 let cond_label = mkVHDLExtId "firstcell"
461 -- if n == 0 or n == len-1
462 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
463 -- Output to tmp[current n]
464 let resname = mkIndexedName tmp_name n_cur
466 argexpr <- MonadState.lift vsType $ varToVHDLExpr start
467 let startassign = mkUncondAssign (Right resname) argexpr
468 app_concsms <- genApplication (Right resname) app_f [Right argexpr]
469 -- Return the conditional generate part
470 return $ AST.GenerateSm cond_label cond_scheme [] (if iter then
477 let cond_label = mkVHDLExtId "othercell"
478 -- if n > 0 or n < len-1
479 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
480 -- Output to tmp[current n]
481 let resname = mkIndexedName tmp_name n_cur
482 -- Input from tmp[previous n]
483 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
484 app_concsms <- genApplication (Right resname) app_f [Right argexpr]
485 -- Return the conditional generate part
486 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
489 -----------------------------------------------------------------------------
490 -- Function to generate VHDL for applications
491 -----------------------------------------------------------------------------
493 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
494 -> CoreSyn.CoreBndr -- ^ The function to apply
495 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
496 -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements
497 genApplication dst f args = do
498 case Var.globalIdVarDetails f of
499 IdInfo.DataConWorkId dc -> case dst of
500 -- It's a datacon. Create a record from its arguments.
502 -- We have the bndr, so we can get at the type
503 labels <- MonadState.lift vsType $ getFieldLabels (Var.varType bndr)
504 args' <- eitherCoreOrExprArgs args
505 return $ zipWith mkassign labels $ args'
507 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
509 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
510 mkUncondAssign (Right sel_name) arg
511 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconstructor application without an original binder"
512 IdInfo.VanillaGlobal -> do
513 -- It's a global value imported from elsewhere. These can be builtin
514 -- functions. Look up the function name in the name table and execute
515 -- the associated builder if there is any and the argument count matches
516 -- (this should always be the case if it typechecks, but just to be
518 case (Map.lookup (varToString f) globalNameTable) of
519 Just (arg_count, builder) ->
520 if length args == arg_count then
523 error $ "\nGenerate.genApplication(VanillaGlobal): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
524 Nothing -> error $ "\nGenerate.genApplication(VanillaGlobal): Using function from another module that is not a known builtin: " ++ pprString f
525 IdInfo.NotGlobalId -> do
526 signatures <- getA vsSignatures
527 -- This is a local id, so it should be a function whose definition we
528 -- have and which can be turned into a component instantiation.
529 case (Map.lookup f signatures) of
531 args' <- eitherCoreOrExprArgs args
532 -- We have a signature, this is a top level binding. Generate a
533 -- component instantiation.
534 let entity_id = ent_id signature
535 -- TODO: Using show here isn't really pretty, but we'll need some
536 -- unique-ish value...
537 let label = "comp_ins_" ++ (either show prettyShow) dst
538 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
539 return [mkComponentInst label entity_id portmaps]
541 -- No signature, so this must be a local variable reference. It
542 -- should have a representable type (and thus, no arguments) and a
543 -- signal should be generated for it. Just generate an
544 -- unconditional assignment here.
545 f' <- MonadState.lift vsType $ varToVHDLExpr f
546 return $ [mkUncondAssign dst f']
548 IdInfo.ClassOpId cls -> do
549 -- FIXME: Not looking for what instance this class op is called for
550 -- Is quite stupid of course.
551 case (Map.lookup (varToString f) globalNameTable) of
552 Just (arg_count, builder) ->
553 if length args == arg_count then
556 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
557 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
558 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
560 -----------------------------------------------------------------------------
561 -- Functions to generate functions dealing with vectors.
562 -----------------------------------------------------------------------------
564 -- Returns the VHDLId of the vector function with the given name for the given
565 -- element type. Generates -- this function if needed.
566 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
567 vectorFunId el_ty fname = do
568 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
569 elemTM <- vhdl_ty error_msg el_ty
570 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
571 -- the VHDLState or something.
572 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
573 typefuns <- getA vsTypeFuns
574 case Map.lookup (OrdType el_ty, fname) typefuns of
575 -- Function already generated, just return it
576 Just (id, _) -> return id
577 -- Function not generated yet, generate it
579 let functions = genUnconsVectorFuns elemTM vectorTM
580 case lookup fname functions of
582 modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, (fst body))
583 mapM_ (vectorFunId el_ty) (snd body)
585 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
587 function_id = mkVHDLExtId fname
589 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
590 -> AST.TypeMark -- ^ type of the vector
591 -> [(String, (AST.SubProgBody, [String]))]
592 genUnconsVectorFuns elemTM vectorTM =
593 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
594 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet],[]))
595 , (headId, (AST.SubProgBody headSpec [] [headExpr],[]))
596 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
597 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
598 , (tailId, (AST.SubProgBody tailSpec [AST.SPVD tailVar] [tailExpr, tailRet],[]))
599 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[]))
600 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
601 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
602 , (emptyId, (AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr],[]))
603 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
604 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
605 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
606 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
607 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
608 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
609 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
610 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
611 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
612 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
613 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
614 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
617 ixPar = AST.unsafeVHDLBasicId "ix"
618 vecPar = AST.unsafeVHDLBasicId "vec"
619 vec1Par = AST.unsafeVHDLBasicId "vec1"
620 vec2Par = AST.unsafeVHDLBasicId "vec2"
621 nPar = AST.unsafeVHDLBasicId "n"
622 iId = AST.unsafeVHDLBasicId "i"
624 aPar = AST.unsafeVHDLBasicId "a"
625 fPar = AST.unsafeVHDLBasicId "f"
626 sPar = AST.unsafeVHDLBasicId "s"
627 resId = AST.unsafeVHDLBasicId "res"
628 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
629 AST.IfaceVarDec ixPar naturalTM] elemTM
630 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
631 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
633 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
634 , AST.IfaceVarDec iPar naturalTM
635 , AST.IfaceVarDec aPar elemTM
637 -- variable res : fsvec_x (0 to vec'length-1);
640 (AST.SubtypeIn vectorTM
641 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
642 [AST.ToRange (AST.PrimLit "0")
643 (AST.PrimName (AST.NAttribute $
644 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
645 (AST.PrimLit "1")) ]))
647 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
648 replaceExpr = AST.NSimple resId AST.:=
649 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
650 AST.PrimName (AST.NSimple aPar) AST.:&:
651 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
652 ((AST.PrimName (AST.NAttribute $
653 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
654 AST.:-: AST.PrimLit "1"))
655 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
656 vecSlice init last = AST.PrimName (AST.NSlice
659 (AST.ToRange init last)))
660 headSpec = AST.Function (mkVHDLExtId headId) [AST.IfaceVarDec vecPar vectorTM] elemTM
662 headExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
663 (AST.NSimple vecPar) [AST.PrimLit "0"])))
664 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
665 -- return vec(vec'length-1);
666 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
668 [AST.PrimName (AST.NAttribute $
669 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
670 AST.:-: AST.PrimLit "1"])))
671 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
672 -- variable res : fsvec_x (0 to vec'length-2);
675 (AST.SubtypeIn vectorTM
676 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
677 [AST.ToRange (AST.PrimLit "0")
678 (AST.PrimName (AST.NAttribute $
679 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
680 (AST.PrimLit "2")) ]))
682 -- resAST.:= vec(0 to vec'length-2)
683 initExpr = AST.NSimple resId AST.:= (vecSlice
685 (AST.PrimName (AST.NAttribute $
686 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
687 AST.:-: AST.PrimLit "2"))
688 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
689 tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
690 -- variable res : fsvec_x (0 to vec'length-2);
693 (AST.SubtypeIn vectorTM
694 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
695 [AST.ToRange (AST.PrimLit "0")
696 (AST.PrimName (AST.NAttribute $
697 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
698 (AST.PrimLit "2")) ]))
700 -- res AST.:= vec(1 to vec'length-1)
701 tailExpr = AST.NSimple resId AST.:= (vecSlice
703 (AST.PrimName (AST.NAttribute $
704 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
705 AST.:-: AST.PrimLit "1"))
706 tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
707 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
708 AST.IfaceVarDec vecPar vectorTM ] vectorTM
709 -- variable res : fsvec_x (0 to n-1);
712 (AST.SubtypeIn vectorTM
713 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
714 [AST.ToRange (AST.PrimLit "0")
715 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
716 (AST.PrimLit "1")) ]))
718 -- res AST.:= vec(0 to n-1)
719 takeExpr = AST.NSimple resId AST.:=
720 (vecSlice (AST.PrimLit "1")
721 (AST.PrimName (AST.NSimple $ nPar) AST.:-: AST.PrimLit "1"))
722 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
723 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
724 AST.IfaceVarDec vecPar vectorTM ] vectorTM
725 -- variable res : fsvec_x (0 to vec'length-n-1);
728 (AST.SubtypeIn vectorTM
729 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
730 [AST.ToRange (AST.PrimLit "0")
731 (AST.PrimName (AST.NAttribute $
732 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
733 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
735 -- res AST.:= vec(n to vec'length-1)
736 dropExpr = AST.NSimple resId AST.:= (vecSlice
737 (AST.PrimName $ AST.NSimple nPar)
738 (AST.PrimName (AST.NAttribute $
739 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
740 AST.:-: AST.PrimLit "1"))
741 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
742 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
743 AST.IfaceVarDec vecPar vectorTM] vectorTM
744 -- variable res : fsvec_x (0 to vec'length);
747 (AST.SubtypeIn vectorTM
748 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
749 [AST.ToRange (AST.PrimLit "0")
750 (AST.PrimName (AST.NAttribute $
751 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
753 plusgtExpr = AST.NSimple resId AST.:=
754 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
755 (AST.PrimName $ AST.NSimple vecPar))
756 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
757 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
760 (AST.SubtypeIn vectorTM Nothing)
761 (Just $ AST.PrimLit "\"\"")
762 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
763 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
765 -- variable res : fsvec_x (0 to 0) := (others => a);
768 (AST.SubtypeIn vectorTM
769 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
770 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
771 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
772 (AST.PrimName $ AST.NSimple aPar)])
773 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
774 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
775 AST.IfaceVarDec aPar elemTM ] vectorTM
776 -- variable res : fsvec_x (0 to n-1) := (others => a);
779 (AST.SubtypeIn vectorTM
780 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
781 [AST.ToRange (AST.PrimLit "0")
782 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
783 (AST.PrimLit "1")) ]))
784 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
785 (AST.PrimName $ AST.NSimple aPar)])
787 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
788 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
789 AST.IfaceVarDec sPar naturalTM,
790 AST.IfaceVarDec nPar naturalTM,
791 AST.IfaceVarDec vecPar vectorTM ] vectorTM
792 -- variable res : fsvec_x (0 to n-1);
795 (AST.SubtypeIn vectorTM
796 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
797 [AST.ToRange (AST.PrimLit "0")
798 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
799 (AST.PrimLit "1")) ])
802 -- for i res'range loop
803 -- res(i) := vec(f+i*s);
805 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) rangeId Nothing) [selAssign]
806 -- res(i) := vec(f+i*s);
807 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
808 (AST.PrimName (AST.NSimple iId) AST.:*:
809 AST.PrimName (AST.NSimple sPar)) in
810 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
811 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
813 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
814 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
815 AST.IfaceVarDec aPar elemTM] vectorTM
816 -- variable res : fsvec_x (0 to vec'length);
819 (AST.SubtypeIn vectorTM
820 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
821 [AST.ToRange (AST.PrimLit "0")
822 (AST.PrimName (AST.NAttribute $
823 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
825 ltplusExpr = AST.NSimple resId AST.:=
826 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
827 (AST.PrimName $ AST.NSimple aPar))
828 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
829 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
830 AST.IfaceVarDec vec2Par vectorTM]
832 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
835 (AST.SubtypeIn vectorTM
836 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
837 [AST.ToRange (AST.PrimLit "0")
838 (AST.PrimName (AST.NAttribute $
839 AST.AttribName (AST.NSimple vec1Par) (mkVHDLBasicId lengthId) Nothing) AST.:+:
840 AST.PrimName (AST.NAttribute $
841 AST.AttribName (AST.NSimple vec2Par) (mkVHDLBasicId lengthId) Nothing) AST.:-:
844 plusplusExpr = AST.NSimple resId AST.:=
845 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
846 (AST.PrimName $ AST.NSimple vec2Par))
847 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
848 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
849 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
850 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
851 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
852 AST.IfaceVarDec aPar elemTM ] vectorTM
853 -- variable res : fsvec_x (0 to vec'length-1);
856 (AST.SubtypeIn vectorTM
857 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
858 [AST.ToRange (AST.PrimLit "0")
859 (AST.PrimName (AST.NAttribute $
860 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
861 (AST.PrimLit "1")) ]))
863 -- res := a & init(vec)
864 shiftlExpr = AST.NSimple resId AST.:=
865 (AST.PrimName (AST.NSimple aPar) AST.:&:
866 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
867 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
868 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
869 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
870 AST.IfaceVarDec aPar elemTM ] vectorTM
871 -- variable res : fsvec_x (0 to vec'length-1);
874 (AST.SubtypeIn vectorTM
875 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
876 [AST.ToRange (AST.PrimLit "0")
877 (AST.PrimName (AST.NAttribute $
878 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
879 (AST.PrimLit "1")) ]))
881 -- res := tail(vec) & a
882 shiftrExpr = AST.NSimple resId AST.:=
883 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
884 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
885 (AST.PrimName (AST.NSimple aPar)))
887 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
888 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
889 -- return vec'length = 0
890 nullExpr = AST.ReturnSm (Just $
891 AST.PrimName (AST.NAttribute $
892 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:=:
894 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
895 -- variable res : fsvec_x (0 to vec'length-1);
898 (AST.SubtypeIn vectorTM
899 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
900 [AST.ToRange (AST.PrimLit "0")
901 (AST.PrimName (AST.NAttribute $
902 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
903 (AST.PrimLit "1")) ]))
905 -- if null(vec) then res := vec else res := last(vec) & init(vec)
906 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
907 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
908 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
910 (Just $ AST.Else [rotlExprRet])
912 AST.NSimple resId AST.:=
913 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
914 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
915 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
916 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
917 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
918 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
919 -- variable res : fsvec_x (0 to vec'length-1);
922 (AST.SubtypeIn vectorTM
923 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
924 [AST.ToRange (AST.PrimLit "0")
925 (AST.PrimName (AST.NAttribute $
926 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
927 (AST.PrimLit "1")) ]))
929 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
930 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
931 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
932 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
934 (Just $ AST.Else [rotrExprRet])
936 AST.NSimple resId AST.:=
937 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
938 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
939 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
940 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
941 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
942 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
945 (AST.SubtypeIn vectorTM
946 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
947 [AST.ToRange (AST.PrimLit "0")
948 (AST.PrimName (AST.NAttribute $
949 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
950 (AST.PrimLit "1")) ]))
952 -- for i in 0 to res'range loop
953 -- res(vec'length-i-1) := vec(i);
956 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) rangeId Nothing) [reverseAssign]
957 -- res(vec'length-i-1) := vec(i);
958 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
959 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
960 [AST.PrimName $ AST.NSimple iId]))
961 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
962 (mkVHDLBasicId lengthId) Nothing) AST.:-:
963 AST.PrimName (AST.NSimple iId) AST.:-:
966 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
968 -----------------------------------------------------------------------------
969 -- A table of builtin functions
970 -----------------------------------------------------------------------------
972 -- | The builtin functions we support. Maps a name to an argument count and a
974 globalNameTable :: NameTable
975 globalNameTable = Map.fromList
976 [ (exId , (2, genFCall False ) )
977 , (replaceId , (3, genFCall False ) )
978 , (headId , (1, genFCall True ) )
979 , (lastId , (1, genFCall True ) )
980 , (tailId , (1, genFCall False ) )
981 , (initId , (1, genFCall False ) )
982 , (takeId , (2, genFCall False ) )
983 , (dropId , (2, genFCall False ) )
984 , (selId , (4, genFCall False ) )
985 , (plusgtId , (2, genFCall False ) )
986 , (ltplusId , (2, genFCall False ) )
987 , (plusplusId , (2, genFCall False ) )
988 , (mapId , (2, genMap ) )
989 , (zipWithId , (3, genZipWith ) )
990 , (foldlId , (3, genFoldl ) )
991 , (foldrId , (3, genFoldr ) )
992 , (zipId , (2, genZip ) )
993 , (unzipId , (1, genUnzip ) )
994 , (shiftlId , (2, genFCall False ) )
995 , (shiftrId , (2, genFCall False ) )
996 , (rotlId , (1, genFCall False ) )
997 , (rotrId , (1, genFCall False ) )
998 , (concatId , (1, genConcat ) )
999 , (reverseId , (1, genFCall False ) )
1000 , (iteratenId , (3, genIteraten ) )
1001 , (iterateId , (2, genIterate ) )
1002 , (generatenId , (3, genGeneraten ) )
1003 , (generateId , (2, genGenerate ) )
1004 , (emptyId , (0, genFCall False ) )
1005 , (singletonId , (1, genFCall False ) )
1006 , (copynId , (2, genFCall False ) )
1007 , (copyId , (1, genCopy ) )
1008 , (lengthTId , (1, genFCall False ) )
1009 , (nullId , (1, genFCall False ) )
1010 , (hwxorId , (2, genOperator2 AST.Xor ) )
1011 , (hwandId , (2, genOperator2 AST.And ) )
1012 , (hworId , (2, genOperator2 AST.Or ) )
1013 , (hwnotId , (1, genOperator1 AST.Not ) )
1014 , (plusId , (2, genOperator2 (AST.:+:) ) )
1015 , (timesId , (2, genOperator2 (AST.:*:) ) )
1016 , (negateId , (1, genNegation ) )
1017 , (minusId , (2, genOperator2 (AST.:-:) ) )
1018 , (fromSizedWordId , (1, genFromSizedWord ) )
1019 , (fromIntegerId , (1, genFromInteger ) )