4 import qualified Control.Monad as Monad
5 import qualified Data.Map as Map
11 import qualified ForSyDe.Backend.VHDL.AST as AST
25 -- | A function to wrap a builder-like function that expects its arguments to
28 (dst -> func -> [AST.Expr] -> res)
29 -> (dst -> func -> [CoreSyn.CoreExpr] -> res)
30 genExprArgs wrap dst func args = wrap dst func args'
31 where args' = map (varToVHDLExpr.exprToVar) args
33 -- | A function to wrap a builder-like function that expects its arguments to
36 (dst -> func -> [Var.Var] -> res)
37 -> (dst -> func -> [CoreSyn.CoreExpr] -> res)
38 genVarArgs wrap dst func args = wrap dst func args'
39 where args' = map exprToVar args
41 -- | A function to wrap a builder-like function that produces an expression
42 -- and expects it to be assigned to the destination.
44 (CoreSyn.CoreBndr -> func -> [arg] -> VHDLSession AST.Expr)
45 -> (CoreSyn.CoreBndr -> func -> [arg] -> VHDLSession [AST.ConcSm])
46 genExprRes wrap dst func args = do
47 expr <- wrap dst func args
48 return $ [mkUncondAssign (Left dst) expr]
50 -- | Generate a binary operator application. The first argument should be a
51 -- constructor from the AST.Expr type, e.g. AST.And.
52 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
53 genOperator2 op = genExprArgs $ genExprRes (genOperator2' op)
54 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
55 genOperator2' op res f [arg1, arg2] = return $ op arg1 arg2
57 -- | Generate a unary operator application
58 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
59 genOperator1 op = genExprArgs $ genExprRes (genOperator1' op)
60 genOperator1' :: (AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
61 genOperator1' op res f [arg] = return $ op arg
63 -- | Generate a function call from the destination binder, function name and a
64 -- list of expressions (its arguments)
65 genFCall :: BuiltinBuilder
66 genFCall = genExprArgs $ genExprRes genFCall'
67 genFCall' :: CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
68 genFCall' res f args = do
69 let fname = varToString f
70 let el_ty = (tfvec_elem . Var.varType) res
71 id <- vectorFunId el_ty fname
72 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
73 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
75 -- | Generate a generate statement for the builtin function "map"
76 genMap :: BuiltinBuilder
77 genMap = genVarArgs genMap'
78 genMap' res f [mapped_f, arg] = do
79 signatures <- getA vsSignatures
80 let entity = Maybe.fromMaybe
81 (error $ "Using function '" ++ (varToString mapped_f) ++ "' without signature? This should not happen!")
82 (Map.lookup mapped_f signatures)
84 -- Setup the generate scheme
85 len = (tfvec_len . Var.varType) res
86 label = mkVHDLExtId ("mapVector" ++ (varToString res))
87 nPar = AST.unsafeVHDLBasicId "n"
88 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
89 genScheme = AST.ForGn nPar range
90 -- Get the entity name and port names
91 entity_id = ent_id entity
92 argports = map (Monad.liftM fst) (ent_args entity)
93 resport = (Monad.liftM fst) (ent_res entity)
95 inport = mkAssocElemIndexed (argports!!0) (varToVHDLId arg) nPar
96 outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
97 portassigns = Maybe.catMaybes [inport,outport]
98 -- Generate the portmap
99 mapLabel = "map" ++ (AST.fromVHDLId entity_id)
100 compins = mkComponentInst mapLabel entity_id portassigns
101 -- Return the generate functions
102 genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
106 genZipWith :: BuiltinBuilder
107 genZipWith = genVarArgs genZipWith'
108 genZipWith' res f args@[zipped_f, arg1, arg2] = do
109 signatures <- getA vsSignatures
110 let entity = Maybe.fromMaybe
111 (error $ "Using function '" ++ (varToString zipped_f) ++ "' without signature? This should not happen!")
112 (Map.lookup zipped_f signatures)
114 -- Setup the generate scheme
115 len = (tfvec_len . Var.varType) res
116 label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
117 nPar = AST.unsafeVHDLBasicId "n"
118 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
119 genScheme = AST.ForGn nPar range
120 -- Get the entity name and port names
121 entity_id = ent_id entity
122 argports = map (Monad.liftM fst) (ent_args entity)
123 resport = (Monad.liftM fst) (ent_res entity)
125 inport1 = mkAssocElemIndexed (argports!!0) (varToVHDLId arg1) nPar
126 inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId arg2) nPar
127 outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
128 portassigns = Maybe.catMaybes [inport1,inport2,outport]
129 -- Generate the portmap
130 mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id)
131 compins = mkComponentInst mapLabel entity_id portassigns
132 -- Return the generate functions
133 genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
137 genFoldl :: BuiltinBuilder
138 genFoldl = genVarArgs genFoldl'
139 genFoldl' resVal f [folded_f, startVal, inVec] = do
140 signatures <- getA vsSignatures
141 let entity = Maybe.fromMaybe
142 (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!")
143 (Map.lookup folded_f signatures)
144 let (vec, _) = splitAppTy (Var.varType inVec)
145 let vecty = Type.mkAppTy vec (Var.varType startVal)
146 vecType <- vhdl_ty vecty
147 -- Setup the generate scheme
148 let len = (tfvec_len . Var.varType) inVec
149 let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
150 let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
151 let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
152 let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range
153 -- Make the intermediate vector
154 let tmpId = mkVHDLExtId "tmp"
155 let tmpVec = AST.BDISD $ AST.SigDec tmpId vecType Nothing
156 -- Get the entity name and port names
157 let entity_id = ent_id entity
158 let argports = map (Monad.liftM fst) (ent_args entity)
159 let resport = (Monad.liftM fst) (ent_res entity)
160 -- Generate the output assignment
161 let assign = [mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName
162 (AST.NSimple tmpId) [AST.PrimLit $ show (len-1)])))]
163 -- Return the generate functions
164 let genSm = AST.CSGSm $ AST.GenerateSm genlabel genScheme []
165 [ AST.CSGSm (genFirstCell (entity_id, argports, resport)
166 [startVal, inVec, resVal])
167 , AST.CSGSm (genOtherCell (entity_id, argports, resport)
168 [startVal, inVec, resVal])
170 return $ if len > 0 then
171 [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] (genSm : assign)]
173 [mkUncondAssign (Left resVal) (AST.PrimName $ AST.NSimple (varToVHDLId startVal))]
175 genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
177 cellLabel = mkVHDLExtId "firstcell"
178 cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0"))
179 tmpId = mkVHDLExtId "tmp"
180 nPar = AST.unsafeVHDLBasicId "n"
182 inport1 = mkAssocElem (argports!!0) (varToString startVal)
183 inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
184 outport = mkAssocElemIndexed resport tmpId nPar
185 portassigns = Maybe.catMaybes [inport1,inport2,outport]
186 -- Generate the portmap
187 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
188 compins = mkComponentInst mapLabel entity_id portassigns
189 -- Return the generate functions
190 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
191 genOtherCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
193 len = (tfvec_len . Var.varType) inVec
194 cellLabel = mkVHDLExtId "othercell"
195 cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:/=: (AST.PrimLit "0"))
196 -- ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1)))
197 tmpId = mkVHDLExtId "tmp"
198 nPar = AST.unsafeVHDLBasicId "n"
200 inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
201 inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
202 outport = mkAssocElemIndexed resport tmpId nPar
203 portassigns = Maybe.catMaybes [inport1,inport2,outport]
204 -- Generate the portmap
205 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
206 compins = mkComponentInst mapLabel entity_id portassigns
207 -- Return the generate functions
208 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
210 -- Returns the VHDLId of the vector function with the given name for the given
211 -- element type. Generates -- this function if needed.
212 vectorFunId :: Type.Type -> String -> VHDLSession AST.VHDLId
213 vectorFunId el_ty fname = do
214 elemTM <- vhdl_ty el_ty
215 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
216 -- the VHDLState or something.
217 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
218 typefuns <- getA vsTypeFuns
219 case Map.lookup (OrdType el_ty, fname) typefuns of
220 -- Function already generated, just return it
221 Just (id, _) -> return id
222 -- Function not generated yet, generate it
224 let functions = genUnconsVectorFuns elemTM vectorTM
225 case lookup fname functions of
227 modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, body)
229 Nothing -> error $ "I don't know how to generate vector function " ++ fname
231 function_id = mkVHDLExtId fname
233 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
234 -> AST.TypeMark -- ^ type of the vector
235 -> [(String, AST.SubProgBody)]
236 genUnconsVectorFuns elemTM vectorTM =
237 [ (exId, AST.SubProgBody exSpec [] [exExpr])
238 , (replaceId, AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet])
239 , (headId, AST.SubProgBody headSpec [] [headExpr])
240 , (lastId, AST.SubProgBody lastSpec [] [lastExpr])
241 , (initId, AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet])
242 , (tailId, AST.SubProgBody tailSpec [AST.SPVD tailVar] [tailExpr, tailRet])
243 , (takeId, AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet])
244 , (dropId, AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet])
245 , (plusgtId, AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet])
246 , (emptyId, AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr])
247 , (singletonId, AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet])
248 , (copyId, AST.SubProgBody copySpec [AST.SPVD copyVar] [copyExpr])
251 ixPar = AST.unsafeVHDLBasicId "ix"
252 vecPar = AST.unsafeVHDLBasicId "vec"
253 nPar = AST.unsafeVHDLBasicId "n"
254 iId = AST.unsafeVHDLBasicId "i"
256 aPar = AST.unsafeVHDLBasicId "a"
257 resId = AST.unsafeVHDLBasicId "res"
258 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
259 AST.IfaceVarDec ixPar naturalTM] elemTM
260 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
261 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
263 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
264 , AST.IfaceVarDec iPar naturalTM
265 , AST.IfaceVarDec aPar elemTM
267 -- variable res : fsvec_x (0 to vec'length-1);
270 (AST.SubtypeIn vectorTM
271 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
272 [AST.ToRange (AST.PrimLit "0")
273 (AST.PrimName (AST.NAttribute $
274 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
275 (AST.PrimLit "1")) ]))
277 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
278 replaceExpr = AST.NSimple resId AST.:=
279 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
280 AST.PrimName (AST.NSimple aPar) AST.:&:
281 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
282 ((AST.PrimName (AST.NAttribute $
283 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
284 AST.:-: AST.PrimLit "1"))
285 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
286 vecSlice init last = AST.PrimName (AST.NSlice
289 (AST.ToRange init last)))
290 headSpec = AST.Function (mkVHDLExtId headId) [AST.IfaceVarDec vecPar vectorTM] elemTM
292 headExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
293 (AST.NSimple vecPar) [AST.PrimLit "0"])))
294 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
295 -- return vec(vec'length-1);
296 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
298 [AST.PrimName (AST.NAttribute $
299 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
300 AST.:-: AST.PrimLit "1"])))
301 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
302 -- variable res : fsvec_x (0 to vec'length-2);
305 (AST.SubtypeIn vectorTM
306 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
307 [AST.ToRange (AST.PrimLit "0")
308 (AST.PrimName (AST.NAttribute $
309 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
310 (AST.PrimLit "2")) ]))
312 -- resAST.:= vec(0 to vec'length-2)
313 initExpr = AST.NSimple resId AST.:= (vecSlice
315 (AST.PrimName (AST.NAttribute $
316 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
317 AST.:-: AST.PrimLit "2"))
318 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
319 tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
320 -- variable res : fsvec_x (0 to vec'length-2);
323 (AST.SubtypeIn vectorTM
324 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
325 [AST.ToRange (AST.PrimLit "0")
326 (AST.PrimName (AST.NAttribute $
327 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
328 (AST.PrimLit "2")) ]))
330 -- res AST.:= vec(1 to vec'length-1)
331 tailExpr = AST.NSimple resId AST.:= (vecSlice
333 (AST.PrimName (AST.NAttribute $
334 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
335 AST.:-: AST.PrimLit "1"))
336 tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
337 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
338 AST.IfaceVarDec vecPar vectorTM ] vectorTM
339 -- variable res : fsvec_x (0 to n-1);
342 (AST.SubtypeIn vectorTM
343 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
344 [AST.ToRange (AST.PrimLit "0")
345 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
346 (AST.PrimLit "1")) ]))
348 -- res AST.:= vec(0 to n-1)
349 takeExpr = AST.NSimple resId AST.:=
350 (vecSlice (AST.PrimLit "1")
351 (AST.PrimName (AST.NSimple $ nPar) AST.:-: AST.PrimLit "1"))
352 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
353 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
354 AST.IfaceVarDec vecPar vectorTM ] vectorTM
355 -- variable res : fsvec_x (0 to vec'length-n-1);
358 (AST.SubtypeIn vectorTM
359 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
360 [AST.ToRange (AST.PrimLit "0")
361 (AST.PrimName (AST.NAttribute $
362 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
363 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
365 -- res AST.:= vec(n to vec'length-1)
366 dropExpr = AST.NSimple resId AST.:= (vecSlice
367 (AST.PrimName $ AST.NSimple nPar)
368 (AST.PrimName (AST.NAttribute $
369 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
370 AST.:-: AST.PrimLit "1"))
371 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
372 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
373 AST.IfaceVarDec vecPar vectorTM] vectorTM
374 -- variable res : fsvec_x (0 to vec'length);
377 (AST.SubtypeIn vectorTM
378 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
379 [AST.ToRange (AST.PrimLit "0")
380 (AST.PrimName (AST.NAttribute $
381 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
383 plusgtExpr = AST.NSimple resId AST.:=
384 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
385 (AST.PrimName $ AST.NSimple vecPar))
386 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
387 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
390 (AST.SubtypeIn vectorTM Nothing)
391 (Just $ AST.PrimLit "\"\"")
392 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
393 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
395 -- variable res : fsvec_x (0 to 0) := (others => a);
398 (AST.SubtypeIn vectorTM
399 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
400 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
401 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
402 (AST.PrimName $ AST.NSimple aPar)])
403 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
404 copySpec = AST.Function (mkVHDLExtId copyId) [AST.IfaceVarDec nPar naturalTM,
405 AST.IfaceVarDec aPar elemTM ] vectorTM
406 -- variable res : fsvec_x (0 to n-1) := (others => a);
409 (AST.SubtypeIn vectorTM
410 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
411 [AST.ToRange (AST.PrimLit "0")
412 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
413 (AST.PrimLit "1")) ]))
414 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
415 (AST.PrimName $ AST.NSimple aPar)])
417 copyExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)