1 module CLasH.VHDL.Generate where
4 import qualified Data.List as List
5 import qualified Data.Map as Map
6 import qualified Control.Monad as Monad
8 import qualified Data.Either as Either
10 import Data.Accessor.MonadState as MonadState
14 import qualified Language.VHDL.AST as AST
17 import qualified CoreSyn
21 import qualified IdInfo
22 import qualified Literal
24 import qualified TyCon
27 import CLasH.Translator.TranslatorTypes
28 import CLasH.VHDL.Constants
29 import CLasH.VHDL.VHDLTypes
30 import CLasH.VHDL.VHDLTools
31 import CLasH.Utils as Utils
32 import CLasH.Utils.Core.CoreTools
33 import CLasH.Utils.Pretty
34 import qualified CLasH.Normalize as Normalize
36 -----------------------------------------------------------------------------
37 -- Functions to generate VHDL for user-defined functions.
38 -----------------------------------------------------------------------------
40 -- | Create an entity for a given function
43 -> TranslatorSession Entity -- ^ The resulting entity
45 getEntity fname = Utils.makeCached fname tsEntities $ do
46 expr <- Normalize.getNormalized fname
47 -- Split the normalized expression
48 let (args, binds, res) = Normalize.splitNormalized expr
49 -- Generate ports for all non-empty types
50 args' <- catMaybesM $ mapM mkMap args
51 -- TODO: Handle Nothing
53 count <- getA tsEntityCounter
54 let vhdl_id = mkVHDLBasicId $ varToString fname ++ "Component_" ++ show count
55 putA tsEntityCounter (count + 1)
56 let ent_decl = createEntityAST vhdl_id args' res'
57 let signature = Entity vhdl_id args' res' ent_decl
61 --[(SignalId, SignalInfo)]
63 -> TranslatorSession (Maybe Port)
66 --info = Maybe.fromMaybe
67 -- (error $ "Signal not found in the name map? This should not happen!")
69 -- Assume the bndr has a valid VHDL id already
72 error_msg = "\nVHDL.createEntity.mkMap: Can not create entity: " ++ pprString fname ++ "\nbecause no type can be created for port: " ++ pprString bndr
74 type_mark_maybe <- MonadState.lift tsType $ vhdlTy error_msg ty
75 case type_mark_maybe of
76 Just type_mark -> return $ Just (id, type_mark)
77 Nothing -> return Nothing
80 -- | Create the VHDL AST for an entity
82 AST.VHDLId -- ^ The name of the function
83 -> [Port] -- ^ The entity's arguments
84 -> Maybe Port -- ^ The entity's result
85 -> AST.EntityDec -- ^ The entity with the ent_decl filled in as well
87 createEntityAST vhdl_id args res =
88 AST.EntityDec vhdl_id ports
90 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
91 ports = map (mkIfaceSigDec AST.In) args
92 ++ (Maybe.maybeToList res_port)
93 ++ [clk_port,resetn_port]
94 -- Add a clk port if we have state
95 clk_port = AST.IfaceSigDec clockId AST.In std_logicTM
96 resetn_port = AST.IfaceSigDec resetId AST.In std_logicTM
97 res_port = fmap (mkIfaceSigDec AST.Out) res
99 -- | Create a port declaration
101 AST.Mode -- ^ The mode for the port (In / Out)
102 -> Port -- ^ The id and type for the port
103 -> AST.IfaceSigDec -- ^ The resulting port declaration
105 mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
107 -- | Create an architecture for a given function
109 CoreSyn.CoreBndr -- ^ The function to get an architecture for
110 -> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
111 -- ^ The architecture for this function
113 getArchitecture fname = Utils.makeCached fname tsArchitectures $ do
114 expr <- Normalize.getNormalized fname
115 -- Split the normalized expression
116 let (args, binds, res) = Normalize.splitNormalized expr
118 -- Get the entity for this function
119 signature <- getEntity fname
120 let entity_id = ent_id signature
122 -- Create signal declarations for all binders in the let expression, except
123 -- for the output port (that will already have an output port declared in
125 sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
126 let sig_decs = Maybe.catMaybes $ sig_dec_maybes
127 -- Process each bind, resulting in info about state variables and concurrent
129 (state_vars, sms) <- Monad.mapAndUnzipM dobind binds
130 let (in_state_maybes, out_state_maybes) = unzip state_vars
131 let (statementss, used_entitiess) = unzip sms
132 -- Get initial state, if it's there
133 initSmap <- getA tsInitStates
134 let init_state = Map.lookup fname initSmap
135 -- Create a state proc, if needed
136 (state_proc, resbndr) <- case (Maybe.catMaybes in_state_maybes, Maybe.catMaybes out_state_maybes, init_state) of
137 ([in_state], [out_state], Nothing) -> do
138 nonEmpty <- hasNonEmptyType in_state
139 if nonEmpty then error ("No initial state defined for: " ++ show fname) else return ([],[])
140 ([in_state], [out_state], Just resetval) -> mkStateProcSm (in_state, out_state,resetval)
141 ([], [], Just _) -> error $ "Initial state defined for state-less function: " ++ show fname
142 ([], [], Nothing) -> return ([],[])
143 (ins, outs, res) -> error $ "Weird use of state in " ++ show fname ++ ". In: " ++ show ins ++ " Out: " ++ show outs
144 -- Join the create statements and the (optional) state_proc
145 let statements = concat statementss ++ state_proc
146 -- Create the architecture
147 let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) statements
148 let used_entities = (concat used_entitiess) ++ resbndr
149 return (arch, used_entities)
151 dobind :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The bind to process
152 -> TranslatorSession ((Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreBndr), ([AST.ConcSm], [CoreSyn.CoreBndr]))
153 -- ^ ((Input state variable, output state variable), (statements, used entities))
154 -- newtype unpacking is just a cast
155 dobind (bndr, unpacked@(CoreSyn.Cast packed coercion))
156 | hasStateType packed && not (hasStateType unpacked)
157 = return ((Just bndr, Nothing), ([], []))
158 -- With simplCore, newtype packing is just a cast
159 dobind (bndr, packed@(CoreSyn.Cast unpacked@(CoreSyn.Var state) coercion))
160 | hasStateType packed && not (hasStateType unpacked)
161 = return ((Nothing, Just state), ([], []))
162 -- Without simplCore, newtype packing uses a data constructor
163 dobind (bndr, (CoreSyn.App (CoreSyn.App (CoreSyn.Var con) (CoreSyn.Type _)) (CoreSyn.Var state)))
165 = return ((Nothing, Just state), ([], []))
166 -- Anything else is handled by mkConcSm
169 return ((Nothing, Nothing), sms)
172 (CoreSyn.CoreBndr, CoreSyn.CoreBndr, CoreSyn.CoreBndr) -- ^ The current state, new state and reset variables
173 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]) -- ^ The resulting statements
174 mkStateProcSm (old, new, res) = do
175 let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString res
176 type_mark_old_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType old)
177 let type_mark_old = Maybe.fromJust type_mark_old_maybe
178 type_mark_res_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType res)
179 let type_mark_res' = Maybe.fromJust type_mark_res_maybe
180 let type_mark_res = if type_mark_old == type_mark_res' then
183 error $ "Initial state has different type than state type, state type: " ++ show type_mark_old ++ ", init type: " ++ show type_mark_res'
184 let resvalid = mkVHDLExtId $ varToString res ++ "val"
185 let resvaldec = AST.BDISD $ AST.SigDec resvalid type_mark_res Nothing
186 let reswform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple resvalid) Nothing]
187 let res_assign = AST.SigAssign (varToVHDLName old) reswform
188 let blocklabel = mkVHDLBasicId $ "state"
189 let statelabel = mkVHDLBasicId $ "stateupdate"
190 let rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
191 let wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
192 let clk_assign = AST.SigAssign (varToVHDLName old) wform
193 let rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
194 let resetn_is_low = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
195 signature <- getEntity res
196 let entity_id = ent_id signature
197 let reslabel = "resetval_" ++ ((prettyShow . varToVHDLName) res)
198 let portmaps = mkAssocElems [] (AST.NSimple resvalid) signature
199 let reset_statement = mkComponentInst reslabel entity_id portmaps
200 let clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
201 let statement = AST.IfSm resetn_is_low [res_assign] clk_statement Nothing
202 let stateupdate = AST.CSPSm $ AST.ProcSm statelabel [clockId,resetId,resvalid] [statement]
203 let block = AST.CSBSm $ AST.BlockSm blocklabel [] (AST.PMapAspect []) [resvaldec] [reset_statement,stateupdate]
204 return ([block],[res])
206 -- | Transforms a core binding into a VHDL concurrent statement
208 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
209 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
210 -- ^ The corresponding VHDL concurrent statements and entities
214 -- Ignore Cast expressions, they should not longer have any meaning as long as
215 -- the type works out. Throw away state repacking
216 mkConcSm (bndr, to@(CoreSyn.Cast from ty))
217 | hasStateType to && hasStateType from
219 mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr)
221 -- Simple a = b assignments are just like applications, but without arguments.
222 -- We can't just generate an unconditional assignment here, since b might be a
223 -- top level binding (e.g., a function with no arguments).
224 mkConcSm (bndr, CoreSyn.Var v) = do
225 genApplication (Left bndr) v []
227 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
228 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
229 let valargs = get_val_args (Var.varType f) args
230 genApplication (Left bndr) f (map Left valargs)
232 -- A single alt case must be a selector. This means the scrutinee is a simple
233 -- variable, the alternative is a dataalt with a single non-wild binder that
235 mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt]))
236 -- Don't generate VHDL for substate extraction
237 | hasStateType bndr = return ([], [])
240 (CoreSyn.DataAlt dc, bndrs, (CoreSyn.Var sel_bndr)) -> do
241 bndrs' <- Monad.filterM hasNonEmptyType bndrs
242 case List.elemIndex sel_bndr bndrs' of
244 htypeScrt <- MonadState.lift tsType $ mkHTypeEither (Var.varType scrut)
245 htypeBndr <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
246 case htypeScrt == htypeBndr of
248 let sel_name = varToVHDLName scrut
249 let sel_expr = AST.PrimName sel_name
250 return ([mkUncondAssign (Left bndr) sel_expr], [])
253 Right (AggrType _ _) -> do
254 labels <- MonadState.lift tsType $ getFieldLabels (Id.idType scrut)
255 let label = labels!!i
256 let sel_name = mkSelectedName (varToVHDLName scrut) label
257 let sel_expr = AST.PrimName sel_name
258 return ([mkUncondAssign (Left bndr) sel_expr], [])
259 _ -> do -- error $ "DIE!"
260 let sel_name = varToVHDLName scrut
261 let sel_expr = AST.PrimName sel_name
262 return ([mkUncondAssign (Left bndr) sel_expr], [])
263 Nothing -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
265 _ -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
267 -- Multiple case alt are be conditional assignments and have only wild
268 -- binders in the alts and only variables in the case values and a variable
269 -- for a scrutinee. We check the constructor of the second alt, since the
270 -- first is the default case, if there is any.
272 -- mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do
273 -- scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
274 -- altcon <- MonadState.lift tsType $ altconToVHDLExpr con
275 -- let cond_expr = scrut' AST.:=: altcon
276 -- true_expr <- MonadState.lift tsType $ varToVHDLExpr true
277 -- false_expr <- MonadState.lift tsType $ varToVHDLExpr false
278 -- return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], [])
279 mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) _ _ (alt:alts))) = do --error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives"
280 scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
281 -- Omit first condition, which is the default
282 altcons <- MonadState.lift tsType $ mapM (altconToVHDLExpr . (\(con,_,_) -> con)) alts
283 let cond_exprs = map (\x -> scrut' AST.:=: x) altcons
284 -- Rotate expressions to the left, so that the expression related to the default case is the last
285 exprs <- MonadState.lift tsType $ mapM (varToVHDLExpr . (\(_,_,CoreSyn.Var expr) -> expr)) (alts ++ [alt])
286 return ([mkAltsAssign (Left bndr) cond_exprs exprs], [])
288 mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement has does not have a simple variable as scrutinee"
289 mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
291 -----------------------------------------------------------------------------
292 -- Functions to generate VHDL for builtin functions
293 -----------------------------------------------------------------------------
295 -- | A function to wrap a builder-like function that expects its arguments to
297 genExprArgs wrap dst func args = do
298 args' <- argsToVHDLExprs args
301 -- | Turn the all lefts into VHDL Expressions.
302 argsToVHDLExprs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
303 argsToVHDLExprs = catMaybesM . (mapM argToVHDLExpr)
305 argToVHDLExpr :: Either CoreSyn.CoreExpr AST.Expr -> TranslatorSession (Maybe AST.Expr)
306 argToVHDLExpr (Left expr) = MonadState.lift tsType $ do
307 let errmsg = "Generate.argToVHDLExpr: Using non-representable type? Should not happen!"
308 ty_maybe <- vhdlTy errmsg expr
311 vhdl_expr <- varToVHDLExpr $ exprToVar expr
312 return $ Just vhdl_expr
313 Nothing -> return $ Nothing
315 argToVHDLExpr (Right expr) = return $ Just expr
317 -- A function to wrap a builder-like function that generates no component
320 (dst -> func -> args -> TranslatorSession [AST.ConcSm])
321 -> (dst -> func -> args -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]))
322 genNoInsts wrap dst func args = do
323 concsms <- wrap dst func args
326 -- | A function to wrap a builder-like function that expects its arguments to
329 (dst -> func -> [Var.Var] -> res)
330 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
331 genVarArgs wrap dst func args = wrap dst func args'
333 args' = map exprToVar exprargs
334 -- Check (rather crudely) that all arguments are CoreExprs
335 (exprargs, []) = Either.partitionEithers args
337 -- | A function to wrap a builder-like function that expects its arguments to
340 (dst -> func -> [Literal.Literal] -> TranslatorSession [AST.ConcSm])
341 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.ConcSm])
342 genLitArgs wrap dst func args = do
343 hscenv <- MonadState.lift tsType $ getA tsHscEnv
344 let (exprargs, []) = Either.partitionEithers args
345 -- FIXME: Check if we were passed an CoreSyn.App
346 let litargs = concat (map (getLiterals hscenv) exprargs)
347 let args' = map exprToLit litargs
348 concsms <- wrap dst func args'
351 -- | A function to wrap a builder-like function that produces an expression
352 -- and expects it to be assigned to the destination.
354 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession AST.Expr)
355 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession [AST.ConcSm])
356 genExprRes wrap dst func args = do
357 expr <- wrap dst func args
358 return $ [mkUncondAssign dst expr]
360 -- | Generate a binary operator application. The first argument should be a
361 -- constructor from the AST.Expr type, e.g. AST.And.
362 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
363 genOperator2 op = genNoInsts $ genExprArgs $ genExprRes (genOperator2' op)
364 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
365 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
367 -- | Generate a unary operator application
368 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
369 genOperator1 op = genNoInsts $ genExprArgs $ genExprRes (genOperator1' op)
370 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
371 genOperator1' op _ f [arg] = return $ op arg
373 -- | Generate a unary operator application
374 genNegation :: BuiltinBuilder
375 genNegation = genNoInsts $ genVarArgs $ genExprRes genNegation'
376 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession AST.Expr
377 genNegation' _ f [arg] = do
378 arg1 <- MonadState.lift tsType $ varToVHDLExpr arg
379 let ty = Var.varType arg
380 let (tycon, args) = Type.splitTyConApp ty
381 let name = Name.getOccString (TyCon.tyConName tycon)
383 "SizedInt" -> return $ AST.Neg arg1
384 otherwise -> error $ "\nGenerate.genNegation': Negation not allowed for type: " ++ show name
386 -- | Generate a function call from the destination binder, function name and a
387 -- list of expressions (its arguments)
388 genFCall :: Bool -> BuiltinBuilder
389 genFCall switch = genNoInsts $ genExprArgs $ genExprRes (genFCall' switch)
390 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
391 genFCall' switch (Left res) f args = do
392 let fname = varToString f
393 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
394 id <- MonadState.lift tsType $ vectorFunId el_ty fname
395 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
396 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
397 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
399 genFromSizedWord :: BuiltinBuilder
400 genFromSizedWord = genNoInsts $ genExprArgs genFromSizedWord'
401 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
402 genFromSizedWord' (Left res) f args@[arg] = do
403 return $ [mkUncondAssign (Left res) arg]
404 -- let fname = varToString f
405 -- return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
406 -- map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
407 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
409 genResize :: BuiltinBuilder
410 genResize = genNoInsts $ genExprArgs $ genExprRes genResize'
411 genResize' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
412 genResize' (Left res) f [arg] = do {
413 ; let { ty = Var.varType res
414 ; (tycon, args) = Type.splitTyConApp ty
415 ; name = Name.getOccString (TyCon.tyConName tycon)
417 ; len <- case name of
418 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
419 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
420 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
421 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
423 genResize' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
425 -- FIXME: I'm calling genLitArgs which is very specific function,
426 -- which needs to be fixed as well
427 genFromInteger :: BuiltinBuilder
428 genFromInteger = genNoInsts $ genLitArgs $ genExprRes genFromInteger'
429 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> TranslatorSession AST.Expr
430 genFromInteger' (Left res) f lits = do {
431 ; let { ty = Var.varType res
432 ; (tycon, args) = Type.splitTyConApp ty
433 ; name = Name.getOccString (TyCon.tyConName tycon)
435 ; len <- case name of
436 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
437 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
439 ; bound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
440 ; return $ floor (logBase 2 (fromInteger (toInteger (bound)))) + 1
442 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId ; "RangedWord" -> toUnsignedId
443 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
444 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
448 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
450 genSizedInt :: BuiltinBuilder
451 genSizedInt = genFromInteger
454 -- | Generate a Builder for the builtin datacon TFVec
455 genTFVec :: BuiltinBuilder
456 genTFVec (Left res) f [Left (CoreSyn.Let (CoreSyn.Rec letBinders) letRes)] = do {
457 -- Generate Assignments for all the binders
458 ; letAssigns <- mapM genBinderAssign letBinders
459 -- Generate assignments for the result (which might be another let binding)
460 ; (resBinders,resAssignments) <- genResAssign letRes
461 -- Get all the Assigned binders
462 ; let assignedBinders = Maybe.catMaybes (map fst letAssigns)
463 -- Make signal names for all the assigned binders
464 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) (assignedBinders ++ resBinders)
465 -- Assign all the signals to the resulting vector
466 ; let { vecsigns = mkAggregateSignal sigs
467 ; vecassign = mkUncondAssign (Left res) vecsigns
469 -- Generate all the signal declaration for the assigned binders
470 ; sig_dec_maybes <- mapM mkSigDec (assignedBinders ++ resBinders)
471 ; let { sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
472 -- Setup the VHDL Block
473 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
474 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs ((concat (map snd letAssigns)) ++ resAssignments ++ [vecassign])
476 -- Return the block statement coressponding to the TFVec literal
477 ; return $ [AST.CSBSm block]
480 genBinderAssign :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -> TranslatorSession (Maybe CoreSyn.CoreBndr, [AST.ConcSm])
481 -- For now we only translate applications
482 genBinderAssign (bndr, app@(CoreSyn.App _ _)) = do
483 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
484 let valargs = get_val_args (Var.varType f) args
485 apps <- genApplication (Left bndr) f (map Left valargs)
486 return (Just bndr, apps)
487 genBinderAssign _ = return (Nothing,[])
488 genResAssign :: CoreSyn.CoreExpr -> TranslatorSession ([CoreSyn.CoreBndr], [AST.ConcSm])
489 genResAssign app@(CoreSyn.App _ letexpr) = do
491 (CoreSyn.Let (CoreSyn.Rec letbndrs) letres) -> do
492 letapps <- mapM genBinderAssign letbndrs
493 let bndrs = Maybe.catMaybes (map fst letapps)
494 let app = (map snd letapps)
495 (vars, apps) <- genResAssign letres
496 return ((bndrs ++ vars),((concat app) ++ apps))
497 otherwise -> return ([],[])
498 genResAssign _ = return ([],[])
500 genTFVec (Left res) f [Left app@(CoreSyn.App _ _)] = do {
501 ; let { elems = reduceCoreListToHsList app
502 -- Make signal names for all the binders
503 ; binders = map (\expr -> case expr of
505 otherwise -> error $ "\nGenerate.genTFVec: Cannot generate TFVec: "
506 ++ show res ++ ", with elems:\n" ++ show elems ++ "\n" ++ pprString elems) elems
508 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) binders
509 -- Assign all the signals to the resulting vector
510 ; let { vecsigns = mkAggregateSignal sigs
511 ; vecassign = mkUncondAssign (Left res) vecsigns
512 -- Setup the VHDL Block
513 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
514 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [vecassign]
516 -- Return the block statement coressponding to the TFVec literal
517 ; return $ [AST.CSBSm block]
520 genTFVec (Left name) _ [Left xs] = error $ "\nGenerate.genTFVec: Cannot generate TFVec: " ++ show name ++ ", with elems:\n" ++ show xs ++ "\n" ++ pprString xs
522 genTFVec (Right name) _ _ = error $ "\nGenerate.genTFVec: Cannot generate TFVec assigned to VHDLName: " ++ show name
524 -- | Generate a generate statement for the builtin function "map"
525 genMap :: BuiltinBuilder
526 genMap (Left res) f [Left mapped_f, Left (CoreSyn.Var arg)] = do {
527 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
528 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
529 -- we must index it (which we couldn't if it was a VHDL Expr, since only
530 -- VHDLNames can be indexed).
531 -- Setup the generate scheme
532 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
533 -- TODO: Use something better than varToString
534 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
535 ; n_id = mkVHDLBasicId "n"
536 ; n_expr = idToVHDLExpr n_id
537 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
538 ; genScheme = AST.ForGn n_id range
539 -- Create the content of the generate statement: Applying the mapped_f to
540 -- each of the elements in arg, storing to each element in res
541 ; resname = mkIndexedName (varToVHDLName res) n_expr
542 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
543 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
544 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
546 ; (app_concsms, used) <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
547 -- Return the generate statement
548 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
551 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
553 genZipWith :: BuiltinBuilder
554 genZipWith = genVarArgs genZipWith'
555 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
556 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do {
557 -- Setup the generate scheme
558 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
559 -- TODO: Use something better than varToString
560 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
561 ; n_id = mkVHDLBasicId "n"
562 ; n_expr = idToVHDLExpr n_id
563 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
564 ; genScheme = AST.ForGn n_id range
565 -- Create the content of the generate statement: Applying the zipped_f to
566 -- each of the elements in arg1 and arg2, storing to each element in res
567 ; resname = mkIndexedName (varToVHDLName res) n_expr
568 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
569 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
571 ; (app_concsms, used) <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
572 -- Return the generate functions
573 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
576 genFoldl :: BuiltinBuilder
577 genFoldl = genFold True
579 genFoldr :: BuiltinBuilder
580 genFoldr = genFold False
582 genFold :: Bool -> BuiltinBuilder
583 genFold left = genVarArgs (genFold' left)
585 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
586 genFold' left res f args@[folded_f , start ,vec]= do
587 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty (Var.varType vec))
588 genFold'' len left res f args
590 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
591 -- Special case for an empty input vector, just assign start to res
592 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
593 arg <- MonadState.lift tsType $ varToVHDLExpr start
594 return ([mkUncondAssign (Left res) arg], [])
596 genFold'' len left (Left res) f [folded_f, start, vec] = do
598 --len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
599 -- An expression for len-1
600 let len_min_expr = (AST.PrimLit $ show (len-1))
601 -- evec is (TFVec n), so it still needs an element type
602 let (nvec, _) = Type.splitAppTy (Var.varType vec)
603 -- Put the type of the start value in nvec, this will be the type of our
605 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
606 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
607 -- TODO: Handle Nothing
608 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdlTy error_msg tmp_ty
609 -- Setup the generate scheme
610 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
611 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString res))
612 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
613 else AST.DownRange len_min_expr (AST.PrimLit "0")
614 let gen_scheme = AST.ForGn n_id gen_range
615 -- Make the intermediate vector
616 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
617 -- Create the generate statement
618 cells' <- sequence [genFirstCell, genOtherCell]
619 let (cells, useds) = unzip cells'
620 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
621 -- Assign tmp[len-1] or tmp[0] to res
622 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
623 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
624 (mkIndexedName tmp_name (AST.PrimLit "0")))
625 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
626 return ([AST.CSBSm block], concat useds)
628 -- An id for the counter
629 n_id = mkVHDLBasicId "n"
630 n_cur = idToVHDLExpr n_id
631 -- An expression for previous n
632 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
633 else (n_cur AST.:+: (AST.PrimLit "1"))
634 -- An id for the tmp result vector
635 tmp_id = mkVHDLBasicId "tmp"
636 tmp_name = AST.NSimple tmp_id
637 -- Generate parts of the fold
638 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
640 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
641 let cond_label = mkVHDLExtId "firstcell"
642 -- if n == 0 or n == len-1
643 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
644 else (AST.PrimLit $ show (len-1)))
645 -- Output to tmp[current n]
646 let resname = mkIndexedName tmp_name n_cur
648 argexpr1 <- MonadState.lift tsType $ varToVHDLExpr start
649 -- Input from vec[current n]
650 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
651 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
652 [Right argexpr1, Right argexpr2]
654 [Right argexpr2, Right argexpr1]
656 -- Return the conditional generate part
657 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
660 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
661 let cond_label = mkVHDLExtId "othercell"
662 -- if n > 0 or n < len-1
663 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
664 else (AST.PrimLit $ show (len-1)))
665 -- Output to tmp[current n]
666 let resname = mkIndexedName tmp_name n_cur
667 -- Input from tmp[previous n]
668 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
669 -- Input from vec[current n]
670 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
671 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
672 [Right argexpr1, Right argexpr2]
674 [Right argexpr2, Right argexpr1]
676 -- Return the conditional generate part
677 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
679 -- | Generate a generate statement for the builtin function "zip"
680 genZip :: BuiltinBuilder
681 genZip = genNoInsts $ genVarArgs genZip'
682 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
683 genZip' (Left res) f args@[arg1, arg2] = do {
684 -- Setup the generate scheme
685 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
686 -- TODO: Use something better than varToString
687 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
688 ; n_id = mkVHDLBasicId "n"
689 ; n_expr = idToVHDLExpr n_id
690 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
691 ; genScheme = AST.ForGn n_id range
692 ; resname' = mkIndexedName (varToVHDLName res) n_expr
693 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
694 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
696 ; labels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType res))
697 ; let { resnameA = mkSelectedName resname' (labels!!0)
698 ; resnameB = mkSelectedName resname' (labels!!1)
699 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
700 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
702 -- Return the generate functions
703 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
706 -- | Generate a generate statement for the builtin function "fst"
707 genFst :: BuiltinBuilder
708 genFst = genNoInsts $ genVarArgs genFst'
709 genFst' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
710 genFst' (Left res) f args@[arg] = do {
711 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
712 ; let { argexpr' = varToVHDLName arg
713 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!0)
714 ; assign = mkUncondAssign (Left res) argexprA
716 -- Return the generate functions
720 -- | Generate a generate statement for the builtin function "snd"
721 genSnd :: BuiltinBuilder
722 genSnd = genNoInsts $ genVarArgs genSnd'
723 genSnd' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
724 genSnd' (Left res) f args@[arg] = do {
725 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
726 ; let { argexpr' = varToVHDLName arg
727 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!1)
728 ; assign = mkUncondAssign (Left res) argexprB
730 -- Return the generate functions
734 -- | Generate a generate statement for the builtin function "unzip"
735 genUnzip :: BuiltinBuilder
736 genUnzip = genNoInsts $ genVarArgs genUnzip'
737 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
738 genUnzip' (Left res) f args@[arg] = do {
739 -- Setup the generate scheme
740 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
741 -- TODO: Use something better than varToString
742 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
743 ; n_id = mkVHDLBasicId "n"
744 ; n_expr = idToVHDLExpr n_id
745 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
746 ; genScheme = AST.ForGn n_id range
747 ; resname' = varToVHDLName res
748 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
750 ; reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
751 ; arglabels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType arg))
752 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
753 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
754 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
755 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
756 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
757 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
759 -- Return the generate functions
760 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
763 genCopy :: BuiltinBuilder
764 genCopy = genNoInsts $ genVarArgs genCopy'
765 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
766 genCopy' (Left res) f args@[arg] =
768 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
769 (AST.PrimName $ (varToVHDLName arg))]
770 out_assign = mkUncondAssign (Left res) resExpr
774 genConcat :: BuiltinBuilder
775 genConcat = genNoInsts $ genVarArgs genConcat'
776 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
777 genConcat' (Left res) f args@[arg] = do {
778 -- Setup the generate scheme
779 ; len1 <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
780 ; let (_, nvec) = Type.splitAppTy (Var.varType arg)
781 ; len2 <- MonadState.lift tsType $ tfp_to_int $ tfvec_len_ty nvec
782 -- TODO: Use something better than varToString
783 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
784 ; n_id = mkVHDLBasicId "n"
785 ; n_expr = idToVHDLExpr n_id
786 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
787 ; genScheme = AST.ForGn n_id range
788 -- Create the content of the generate statement: Applying the mapped_f to
789 -- each of the elements in arg, storing to each element in res
790 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
791 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
792 ; resname = vecSlice fromRange toRange
793 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
794 ; out_assign = mkUncondAssign (Right resname) argexpr
796 -- Return the generate statement
797 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
800 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
801 (AST.ToRange init last))
803 genIteraten :: BuiltinBuilder
804 genIteraten dst f args = genIterate dst f (tail args)
806 genIterate :: BuiltinBuilder
807 genIterate = genIterateOrGenerate True
809 genGeneraten :: BuiltinBuilder
810 genGeneraten dst f args = genGenerate dst f (tail args)
812 genGenerate :: BuiltinBuilder
813 genGenerate = genIterateOrGenerate False
815 genIterateOrGenerate :: Bool -> BuiltinBuilder
816 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
818 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
819 genIterateOrGenerate' iter (Left res) f args = do
820 len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
821 genIterateOrGenerate'' len iter (Left res) f args
823 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
824 -- Special case for an empty input vector, just assign start to res
825 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return ([mkUncondAssign (Left res) (AST.PrimLit "\"\"")], [])
827 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
829 -- len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
830 -- An expression for len-1
831 let len_min_expr = (AST.PrimLit $ show (len-1))
832 -- -- evec is (TFVec n), so it still needs an element type
833 -- let (nvec, _) = splitAppTy (Var.varType vec)
834 -- -- Put the type of the start value in nvec, this will be the type of our
835 -- -- temporary vector
836 let tmp_ty = Var.varType res
837 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
838 -- TODO: Handle Nothing
839 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdlTy error_msg tmp_ty
840 -- Setup the generate scheme
841 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
842 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
843 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
844 let gen_scheme = AST.ForGn n_id gen_range
845 -- Make the intermediate vector
846 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
847 -- Create the generate statement
848 cells' <- sequence [genFirstCell, genOtherCell]
849 let (cells, useds) = unzip cells'
850 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
851 -- Assign tmp[len-1] or tmp[0] to res
852 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
853 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
854 return ([AST.CSBSm block], concat useds)
856 -- An id for the counter
857 n_id = mkVHDLBasicId "n"
858 n_cur = idToVHDLExpr n_id
859 -- An expression for previous n
860 n_prev = n_cur AST.:-: (AST.PrimLit "1")
861 -- An id for the tmp result vector
862 tmp_id = mkVHDLBasicId "tmp"
863 tmp_name = AST.NSimple tmp_id
864 -- Generate parts of the fold
865 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
867 let cond_label = mkVHDLExtId "firstcell"
868 -- if n == 0 or n == len-1
869 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
870 -- Output to tmp[current n]
871 let resname = mkIndexedName tmp_name n_cur
873 argexpr <- MonadState.lift tsType $ varToVHDLExpr start
874 let startassign = mkUncondAssign (Right resname) argexpr
875 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
876 -- Return the conditional generate part
877 let gensm = AST.GenerateSm cond_label cond_scheme [] (if iter then
885 let cond_label = mkVHDLExtId "othercell"
886 -- if n > 0 or n < len-1
887 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
888 -- Output to tmp[current n]
889 let resname = mkIndexedName tmp_name n_cur
890 -- Input from tmp[previous n]
891 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
892 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
893 -- Return the conditional generate part
894 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
896 genBlockRAM :: BuiltinBuilder
897 genBlockRAM = genNoInsts $ genExprArgs genBlockRAM'
899 genBlockRAM' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
900 genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
902 let (tup,data_out) = Type.splitAppTy (Var.varType res)
903 let (tup',ramvec) = Type.splitAppTy tup
904 let Just realram = Type.coreView ramvec
905 let Just (tycon, types) = Type.splitTyConApp_maybe realram
906 Just ram_vhdl_ty <- MonadState.lift tsType $ vhdlTy "wtf" (head types)
907 -- Make the intermediate vector
908 let ram_dec = AST.BDISD $ AST.SigDec ram_id ram_vhdl_ty Nothing
909 -- Get the data_out name
910 -- reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
911 let resname = varToVHDLName res
912 -- let resname = mkSelectedName resname' (reslabels!!0)
913 let rdaddr_int = genExprFCall (mkVHDLBasicId toIntegerId) rdaddr
914 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName (AST.NSimple ram_id) rdaddr_int
915 let assign = mkUncondAssign (Right resname) argexpr
916 let block_label = mkVHDLExtId ("blockRAM" ++ (varToString res))
917 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [ram_dec] [assign, mkUpdateProcSm]
918 return [AST.CSBSm block]
920 ram_id = mkVHDLBasicId "ram"
921 mkUpdateProcSm :: AST.ConcSm
922 mkUpdateProcSm = AST.CSPSm $ AST.ProcSm proclabel [clockId] [statement]
924 proclabel = mkVHDLBasicId "updateRAM"
925 rising_edge = mkVHDLBasicId "rising_edge"
926 wraddr_int = genExprFCall (mkVHDLBasicId toIntegerId) wraddr
927 ramloc = mkIndexedName (AST.NSimple ram_id) wraddr_int
928 wform = AST.Wform [AST.WformElem data_in Nothing]
929 ramassign = AST.SigAssign ramloc wform
930 rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
931 statement = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
933 genSplit :: BuiltinBuilder
934 genSplit = genNoInsts $ genVarArgs genSplit'
936 genSplit' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
937 genSplit' (Left res) f args@[vecIn] = do {
938 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
939 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vecIn
940 ; let { block_label = mkVHDLExtId ("split" ++ (varToString vecIn))
941 ; halflen = round ((fromIntegral len) / 2)
942 ; rangeL = vecSlice (AST.PrimLit "0") (AST.PrimLit $ show (halflen - 1))
943 ; rangeR = vecSlice (AST.PrimLit $ show halflen) (AST.PrimLit $ show (len - 1))
944 ; resname = varToVHDLName res
945 ; resnameL = mkSelectedName resname (labels!!0)
946 ; resnameR = mkSelectedName resname (labels!!1)
947 ; argexprL = vhdlNameToVHDLExpr rangeL
948 ; argexprR = vhdlNameToVHDLExpr rangeR
949 ; out_assignL = mkUncondAssign (Right resnameL) argexprL
950 ; out_assignR = mkUncondAssign (Right resnameR) argexprR
951 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [out_assignL, out_assignR]
953 ; return [AST.CSBSm block]
956 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
957 (AST.ToRange init last))
958 -----------------------------------------------------------------------------
959 -- Function to generate VHDL for applications
960 -----------------------------------------------------------------------------
962 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
963 -> CoreSyn.CoreBndr -- ^ The function to apply
964 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
965 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
966 -- ^ The corresponding VHDL concurrent statements and entities
968 genApplication dst f args = do
969 case Var.isGlobalId f of
971 top <- isTopLevelBinder f
974 -- Local binder that references a top level binding. Generate a
975 -- component instantiation.
976 signature <- getEntity f
977 args' <- argsToVHDLExprs args
978 let entity_id = ent_id signature
979 -- TODO: Using show here isn't really pretty, but we'll need some
980 -- unique-ish value...
981 let label = "comp_ins_" ++ (either (prettyShow . varToVHDLName) prettyShow) dst
982 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
983 return ([mkComponentInst label entity_id portmaps], [f])
985 -- Not a top level binder, so this must be a local variable reference.
986 -- It should have a representable type (and thus, no arguments) and a
987 -- signal should be generated for it. Just generate an unconditional
989 f' <- MonadState.lift tsType $ varToVHDLExpr f
990 return $ ([mkUncondAssign dst f'], [])
992 case Var.idDetails f of
993 IdInfo.DataConWorkId dc -> case dst of
994 -- It's a datacon. Create a record from its arguments.
996 -- We have the bndr, so we can get at the type
997 htype <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
998 let argsNostate = filter (\x -> not (either hasStateType (\x -> False) x)) args
1001 [arg'] <- argsToVHDLExprs [arg]
1002 return $ ([mkUncondAssign dst arg'], [])
1005 Right (AggrType _ _) -> do
1006 labels <- MonadState.lift tsType $ getFieldLabels (Var.varType bndr)
1007 args' <- argsToVHDLExprs argsNostate
1008 return $ (zipWith mkassign labels $ args', [])
1010 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
1011 mkassign label arg =
1012 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
1013 mkUncondAssign (Right sel_name) arg
1014 _ -> do -- error $ "DIE!"
1015 args' <- argsToVHDLExprs argsNostate
1016 return $ ([mkUncondAssign dst (head args')], [])
1017 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconstructor application without an original binder"
1018 IdInfo.DataConWrapId dc -> case dst of
1019 -- It's a datacon. Create a record from its arguments.
1021 case (Map.lookup (varToString f) globalNameTable) of
1022 Just (arg_count, builder) ->
1023 if length args == arg_count then
1026 error $ "\nGenerate.genApplication(DataConWrapId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1027 Nothing -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper: " ++ (show dc)
1028 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper application without an original binder"
1029 IdInfo.VanillaId -> do
1030 -- It's a global value imported from elsewhere. These can be builtin
1031 -- functions. Look up the function name in the name table and execute
1032 -- the associated builder if there is any and the argument count matches
1033 -- (this should always be the case if it typechecks, but just to be
1035 case (Map.lookup (varToString f) globalNameTable) of
1036 Just (arg_count, builder) ->
1037 if length args == arg_count then
1040 error $ "\nGenerate.genApplication(VanillaId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1042 top <- isTopLevelBinder f
1045 -- Local binder that references a top level binding. Generate a
1046 -- component instantiation.
1047 signature <- getEntity f
1048 args' <- argsToVHDLExprs args
1049 let entity_id = ent_id signature
1050 -- TODO: Using show here isn't really pretty, but we'll need some
1051 -- unique-ish value...
1052 let label = "comp_ins_" ++ (either show prettyShow) dst
1053 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
1054 return ([mkComponentInst label entity_id portmaps], [f])
1056 -- Not a top level binder, so this must be a local variable reference.
1057 -- It should have a representable type (and thus, no arguments) and a
1058 -- signal should be generated for it. Just generate an unconditional
1060 -- FIXME : I DONT KNOW IF THE ABOVE COMMENT HOLDS HERE, SO FOR NOW JUST ERROR!
1061 -- f' <- MonadState.lift tsType $ varToVHDLExpr f
1062 -- return $ ([mkUncondAssign dst f'], [])
1063 errtype <- case dst of
1065 htype <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
1067 Right vhd -> return $ show vhd
1068 error $ ("\nGenerate.genApplication(VanillaId): Using function from another module that is not a known builtin: " ++ (pprString f) ++ "::" ++ errtype)
1069 IdInfo.ClassOpId cls -> do
1070 -- FIXME: Not looking for what instance this class op is called for
1071 -- Is quite stupid of course.
1072 case (Map.lookup (varToString f) globalNameTable) of
1073 Just (arg_count, builder) ->
1074 if length args == arg_count then
1077 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1078 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
1079 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
1081 -----------------------------------------------------------------------------
1082 -- Functions to generate functions dealing with vectors.
1083 -----------------------------------------------------------------------------
1085 -- Returns the VHDLId of the vector function with the given name for the given
1086 -- element type. Generates -- this function if needed.
1087 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
1088 vectorFunId el_ty fname = do
1089 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
1090 -- TODO: Handle the Nothing case?
1091 Just elemTM <- vhdlTy error_msg el_ty
1092 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
1093 -- the VHDLState or something.
1094 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
1095 typefuns <- getA tsTypeFuns
1096 el_htype <- mkHType error_msg el_ty
1097 case Map.lookup (UVecType el_htype, fname) typefuns of
1098 -- Function already generated, just return it
1099 Just (id, _) -> return id
1100 -- Function not generated yet, generate it
1102 let functions = genUnconsVectorFuns elemTM vectorTM
1103 case lookup fname functions of
1105 modA tsTypeFuns $ Map.insert (UVecType el_htype, fname) (function_id, (fst body))
1106 mapM_ (vectorFunId el_ty) (snd body)
1108 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
1110 function_id = mkVHDLExtId fname
1112 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
1113 -> AST.TypeMark -- ^ type of the vector
1114 -> [(String, (AST.SubProgBody, [String]))]
1115 genUnconsVectorFuns elemTM vectorTM =
1116 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
1117 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr1,replaceExpr2,replaceRet],[]))
1118 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
1119 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
1120 , (minimumId, (AST.SubProgBody minimumSpec [] [minimumExpr],[]))
1121 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[minimumId]))
1122 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
1123 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
1124 , (emptyId, (AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr],[]))
1125 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
1126 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
1127 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
1128 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
1129 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
1130 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
1131 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
1132 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
1133 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
1134 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
1135 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
1136 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
1139 ixPar = AST.unsafeVHDLBasicId "ix"
1140 vecPar = AST.unsafeVHDLBasicId "vec"
1141 vec1Par = AST.unsafeVHDLBasicId "vec1"
1142 vec2Par = AST.unsafeVHDLBasicId "vec2"
1143 nPar = AST.unsafeVHDLBasicId "n"
1144 leftPar = AST.unsafeVHDLBasicId "nLeft"
1145 rightPar = AST.unsafeVHDLBasicId "nRight"
1146 iId = AST.unsafeVHDLBasicId "i"
1148 aPar = AST.unsafeVHDLBasicId "a"
1149 fPar = AST.unsafeVHDLBasicId "f"
1150 sPar = AST.unsafeVHDLBasicId "s"
1151 resId = AST.unsafeVHDLBasicId "res"
1152 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
1153 AST.IfaceVarDec ixPar unsignedTM] elemTM
1154 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
1155 (AST.IndexedName (AST.NSimple vecPar) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple $ ixPar)]))
1156 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
1157 , AST.IfaceVarDec iPar unsignedTM
1158 , AST.IfaceVarDec aPar elemTM
1160 -- variable res : fsvec_x (0 to vec'length-1);
1163 (AST.SubtypeIn vectorTM
1164 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1165 [AST.ToRange (AST.PrimLit "0")
1166 (AST.PrimName (AST.NAttribute $
1167 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1168 (AST.PrimLit "1")) ]))
1170 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
1171 replaceExpr1 = AST.NSimple resId AST.:= AST.PrimName (AST.NSimple vecPar)
1172 replaceExpr2 = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple $ iPar)]) AST.:= AST.PrimName (AST.NSimple aPar)
1173 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1174 vecSlice init last = AST.PrimName (AST.NSlice
1176 (AST.NSimple vecPar)
1177 (AST.ToRange init last)))
1178 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
1179 -- return vec(vec'length-1);
1180 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
1181 (AST.NSimple vecPar)
1182 [AST.PrimName (AST.NAttribute $
1183 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1184 AST.:-: AST.PrimLit "1"])))
1185 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1186 -- variable res : fsvec_x (0 to vec'length-2);
1189 (AST.SubtypeIn vectorTM
1190 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1191 [AST.ToRange (AST.PrimLit "0")
1192 (AST.PrimName (AST.NAttribute $
1193 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1194 (AST.PrimLit "2")) ]))
1196 -- resAST.:= vec(0 to vec'length-2)
1197 initExpr = AST.NSimple resId AST.:= (vecSlice
1199 (AST.PrimName (AST.NAttribute $
1200 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1201 AST.:-: AST.PrimLit "2"))
1202 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1203 minimumSpec = AST.Function (mkVHDLExtId minimumId) [AST.IfaceVarDec leftPar naturalTM,
1204 AST.IfaceVarDec rightPar naturalTM ] naturalTM
1205 minimumExpr = AST.IfSm ((AST.PrimName $ AST.NSimple leftPar) AST.:<: (AST.PrimName $ AST.NSimple rightPar))
1206 [AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple leftPar)]
1208 (Just $ AST.Else [minimumExprRet])
1209 where minimumExprRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple rightPar)
1210 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
1211 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1212 -- variable res : fsvec_x (0 to (minimum (n,vec'length))-1);
1213 minLength = AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId minimumId))
1214 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple nPar)
1215 ,Nothing AST.:=>: AST.ADExpr (AST.PrimName (AST.NAttribute $
1216 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]
1219 (AST.SubtypeIn vectorTM
1220 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1221 [AST.ToRange (AST.PrimLit "0")
1223 (AST.PrimLit "1")) ]))
1225 -- res AST.:= vec(0 to n-1)
1226 takeExpr = AST.NSimple resId AST.:=
1227 (vecSlice (AST.PrimLit "0")
1228 (minLength AST.:-: AST.PrimLit "1"))
1229 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1230 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
1231 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1232 -- variable res : fsvec_x (0 to vec'length-n-1);
1235 (AST.SubtypeIn vectorTM
1236 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1237 [AST.ToRange (AST.PrimLit "0")
1238 (AST.PrimName (AST.NAttribute $
1239 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1240 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
1242 -- res AST.:= vec(n to vec'length-1)
1243 dropExpr = AST.NSimple resId AST.:= (vecSlice
1244 (AST.PrimName $ AST.NSimple nPar)
1245 (AST.PrimName (AST.NAttribute $
1246 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1247 AST.:-: AST.PrimLit "1"))
1248 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1249 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
1250 AST.IfaceVarDec vecPar vectorTM] vectorTM
1251 -- variable res : fsvec_x (0 to vec'length);
1254 (AST.SubtypeIn vectorTM
1255 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1256 [AST.ToRange (AST.PrimLit "0")
1257 (AST.PrimName (AST.NAttribute $
1258 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1260 plusgtExpr = AST.NSimple resId AST.:=
1261 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
1262 (AST.PrimName $ AST.NSimple vecPar))
1263 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1264 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
1267 (AST.SubtypeIn vectorTM
1268 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1269 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "-1")]))
1271 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1272 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
1274 -- variable res : fsvec_x (0 to 0) := (others => a);
1277 (AST.SubtypeIn vectorTM
1278 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1279 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
1280 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1281 (AST.PrimName $ AST.NSimple aPar)])
1282 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1283 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
1284 AST.IfaceVarDec aPar elemTM ] vectorTM
1285 -- variable res : fsvec_x (0 to n-1) := (others => a);
1288 (AST.SubtypeIn vectorTM
1289 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1290 [AST.ToRange (AST.PrimLit "0")
1291 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1292 (AST.PrimLit "1")) ]))
1293 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1294 (AST.PrimName $ AST.NSimple aPar)])
1296 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1297 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
1298 AST.IfaceVarDec sPar naturalTM,
1299 AST.IfaceVarDec nPar naturalTM,
1300 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1301 -- variable res : fsvec_x (0 to n-1);
1304 (AST.SubtypeIn vectorTM
1305 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1306 [AST.ToRange (AST.PrimLit "0")
1307 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1308 (AST.PrimLit "1")) ])
1311 -- for i res'range loop
1312 -- res(i) := vec(f+i*s);
1314 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [selAssign]
1315 -- res(i) := vec(f+i*s);
1316 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
1317 (AST.PrimName (AST.NSimple iId) AST.:*:
1318 AST.PrimName (AST.NSimple sPar)) in
1319 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
1320 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
1322 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1323 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
1324 AST.IfaceVarDec aPar elemTM] vectorTM
1325 -- variable res : fsvec_x (0 to vec'length);
1328 (AST.SubtypeIn vectorTM
1329 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1330 [AST.ToRange (AST.PrimLit "0")
1331 (AST.PrimName (AST.NAttribute $
1332 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1334 ltplusExpr = AST.NSimple resId AST.:=
1335 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
1336 (AST.PrimName $ AST.NSimple aPar))
1337 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1338 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
1339 AST.IfaceVarDec vec2Par vectorTM]
1341 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
1344 (AST.SubtypeIn vectorTM
1345 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1346 [AST.ToRange (AST.PrimLit "0")
1347 (AST.PrimName (AST.NAttribute $
1348 AST.AttribName (AST.NSimple vec1Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:+:
1349 AST.PrimName (AST.NAttribute $
1350 AST.AttribName (AST.NSimple vec2Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1353 plusplusExpr = AST.NSimple resId AST.:=
1354 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
1355 (AST.PrimName $ AST.NSimple vec2Par))
1356 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1357 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
1358 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
1359 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
1360 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
1361 AST.IfaceVarDec aPar elemTM ] vectorTM
1362 -- variable res : fsvec_x (0 to vec'length-1);
1365 (AST.SubtypeIn vectorTM
1366 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1367 [AST.ToRange (AST.PrimLit "0")
1368 (AST.PrimName (AST.NAttribute $
1369 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1370 (AST.PrimLit "1")) ]))
1372 -- res := a & init(vec)
1373 shiftlExpr = AST.NSimple resId AST.:=
1374 (AST.PrimName (AST.NSimple aPar) AST.:&:
1375 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1376 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1377 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1378 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
1379 AST.IfaceVarDec aPar elemTM ] vectorTM
1380 -- variable res : fsvec_x (0 to vec'length-1);
1383 (AST.SubtypeIn vectorTM
1384 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1385 [AST.ToRange (AST.PrimLit "0")
1386 (AST.PrimName (AST.NAttribute $
1387 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1388 (AST.PrimLit "1")) ]))
1390 -- res := tail(vec) & a
1391 shiftrExpr = AST.NSimple resId AST.:=
1392 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1393 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1394 (AST.PrimName (AST.NSimple aPar)))
1396 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1397 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
1398 -- return vec'length = 0
1399 nullExpr = AST.ReturnSm (Just $
1400 AST.PrimName (AST.NAttribute $
1401 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:=:
1403 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1404 -- variable res : fsvec_x (0 to vec'length-1);
1407 (AST.SubtypeIn vectorTM
1408 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1409 [AST.ToRange (AST.PrimLit "0")
1410 (AST.PrimName (AST.NAttribute $
1411 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1412 (AST.PrimLit "1")) ]))
1414 -- if null(vec) then res := vec else res := last(vec) & init(vec)
1415 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1416 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1417 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1419 (Just $ AST.Else [rotlExprRet])
1421 AST.NSimple resId AST.:=
1422 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
1423 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1424 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1425 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1426 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1427 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1428 -- variable res : fsvec_x (0 to vec'length-1);
1431 (AST.SubtypeIn vectorTM
1432 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1433 [AST.ToRange (AST.PrimLit "0")
1434 (AST.PrimName (AST.NAttribute $
1435 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1436 (AST.PrimLit "1")) ]))
1438 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
1439 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1440 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1441 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1443 (Just $ AST.Else [rotrExprRet])
1445 AST.NSimple resId AST.:=
1446 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1447 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1448 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
1449 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1450 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1451 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1454 (AST.SubtypeIn vectorTM
1455 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1456 [AST.ToRange (AST.PrimLit "0")
1457 (AST.PrimName (AST.NAttribute $
1458 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1459 (AST.PrimLit "1")) ]))
1461 -- for i in 0 to res'range loop
1462 -- res(vec'length-i-1) := vec(i);
1465 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [reverseAssign]
1466 -- res(vec'length-i-1) := vec(i);
1467 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
1468 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
1469 [AST.PrimName $ AST.NSimple iId]))
1470 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
1471 (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1472 AST.PrimName (AST.NSimple iId) AST.:-:
1475 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1478 -----------------------------------------------------------------------------
1479 -- A table of builtin functions
1480 -----------------------------------------------------------------------------
1482 -- A function that generates VHDL for a builtin function
1483 type BuiltinBuilder =
1484 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
1485 -> CoreSyn.CoreBndr -- ^ The function called
1486 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
1487 -- dictionary arguments).
1488 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1489 -- ^ The corresponding VHDL concurrent statements and entities
1492 -- A map of a builtin function to VHDL function builder
1493 type NameTable = Map.Map String (Int, BuiltinBuilder )
1495 -- | The builtin functions we support. Maps a name to an argument count and a
1496 -- builder function.
1497 globalNameTable :: NameTable
1498 globalNameTable = Map.fromList
1499 [ (exId , (2, genFCall True ) )
1500 , (replaceId , (3, genFCall False ) )
1501 , (headId , (1, genFCall True ) )
1502 , (lastId , (1, genFCall True ) )
1503 , (tailId , (1, genFCall False ) )
1504 , (initId , (1, genFCall False ) )
1505 , (takeId , (2, genFCall False ) )
1506 , (dropId , (2, genFCall False ) )
1507 , (selId , (4, genFCall False ) )
1508 , (plusgtId , (2, genFCall False ) )
1509 , (ltplusId , (2, genFCall False ) )
1510 , (plusplusId , (2, genFCall False ) )
1511 , (mapId , (2, genMap ) )
1512 , (zipWithId , (3, genZipWith ) )
1513 , (foldlId , (3, genFoldl ) )
1514 , (foldrId , (3, genFoldr ) )
1515 , (zipId , (2, genZip ) )
1516 , (unzipId , (1, genUnzip ) )
1517 , (shiftlId , (2, genFCall False ) )
1518 , (shiftrId , (2, genFCall False ) )
1519 , (rotlId , (1, genFCall False ) )
1520 , (rotrId , (1, genFCall False ) )
1521 , (concatId , (1, genConcat ) )
1522 , (reverseId , (1, genFCall False ) )
1523 , (iteratenId , (3, genIteraten ) )
1524 , (iterateId , (2, genIterate ) )
1525 , (generatenId , (3, genGeneraten ) )
1526 , (generateId , (2, genGenerate ) )
1527 , (emptyId , (0, genFCall False ) )
1528 , (singletonId , (1, genFCall False ) )
1529 , (copynId , (2, genFCall False ) )
1530 , (copyId , (1, genCopy ) )
1531 , (lengthTId , (1, genFCall False ) )
1532 , (nullId , (1, genFCall False ) )
1533 , (hwxorId , (2, genOperator2 AST.Xor ) )
1534 , (hwandId , (2, genOperator2 AST.And ) )
1535 , (hworId , (2, genOperator2 AST.Or ) )
1536 , (hwnotId , (1, genOperator1 AST.Not ) )
1537 , (equalityId , (2, genOperator2 (AST.:=:) ) )
1538 , (inEqualityId , (2, genOperator2 (AST.:/=:) ) )
1539 , (ltId , (2, genOperator2 (AST.:<:) ) )
1540 , (lteqId , (2, genOperator2 (AST.:<=:) ) )
1541 , (gtId , (2, genOperator2 (AST.:>:) ) )
1542 , (gteqId , (2, genOperator2 (AST.:>=:) ) )
1543 , (boolOrId , (2, genOperator2 AST.Or ) )
1544 , (boolAndId , (2, genOperator2 AST.And ) )
1545 , (plusId , (2, genOperator2 (AST.:+:) ) )
1546 , (timesId , (2, genOperator2 (AST.:*:) ) )
1547 , (negateId , (1, genNegation ) )
1548 , (minusId , (2, genOperator2 (AST.:-:) ) )
1549 , (fromSizedWordId , (1, genFromSizedWord ) )
1550 , (fromIntegerId , (1, genFromInteger ) )
1551 , (resizeWordId , (1, genResize ) )
1552 , (resizeIntId , (1, genResize ) )
1553 , (sizedIntId , (1, genSizedInt ) )
1554 , (smallIntegerId , (1, genFromInteger ) )
1555 , (fstId , (1, genFst ) )
1556 , (sndId , (1, genSnd ) )
1557 , (blockRAMId , (5, genBlockRAM ) )
1558 , (splitId , (1, genSplit ) )
1559 --, (tfvecId , (1, genTFVec ) )
1560 , (minimumId , (2, error $ "\nFunction name: \"minimum\" is used internally, use another name"))