1 module Alu (main) where
5 main = Sim.simulate exec program initial_state
6 mainIO = Sim.simulateIO exec initial_state
10 (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
11 (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
12 (Low, High, DontCare), -- r0 = z (1)
13 (High, Low, High), -- z = r1 and t (0); t = r1 (1)
14 (High, High, DontCare) -- r1 = z (0)
17 initial_state = (Regs Low High, Low, Low)
22 --type RegisterBankState = (Bit, Bit)
23 data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
26 (RegAddr, Bit, Bit) -> -- (addr, we, d)
27 RegisterBankState -> -- s
28 (RegisterBankState, Bit) -- (s', o)
30 register_bank (Low, Low, _) s = -- Read r0
33 register_bank (High, Low, _) s = -- Read r1
36 register_bank (addr, High, d) s = -- Write
40 r0' = if addr == Low then d else r0
41 r1' = if addr == High then d else r1
48 alu :: AluOp -> Bit -> Bit -> Bit
49 alu High a b = a `hwand` b
50 alu Low a b = a `hwor` b
52 type ExecState = (RegisterBankState, Bit, Bit)
53 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
56 exec (addr, Low, op) s =
60 (reg_s', t') = register_bank (addr, Low, DontCare) reg_s
65 exec (addr, High, op) s =
69 (reg_s', _) = register_bank (addr, High, z) reg_s
72 -- vim: set ts=8 sw=2 sts=2 expandtab: