7 main = Sim.simulate exec program initial_state
8 mainIO = Sim.simulateIO exec initial_state
14 (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
15 (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
16 (Low, High, dontcare), -- r0 = z (1)
17 (High, Low, High), -- z = r1 and t (0); t = r1 (1)
18 (High, High, dontcare) -- r1 = z (0)
21 --initial_state = (Regs Low High, Low, Low)
22 initial_state = ((0, 1), 0, 0)
24 type Word = SizedWord D4
27 type RegisterBankState = (Word, Word)
28 --data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
31 (RegAddr, Bit, Word) -> -- (addr, we, d)
32 RegisterBankState -> -- s
33 (RegisterBankState, Word) -- (s', o)
35 register_bank (Low, Low, _) s = -- Read r0
39 register_bank (High, Low, _) s = -- Read r1
43 register_bank (addr, High, d) s = -- Write
48 r0' = case addr of Low -> d; High -> r0
49 r1' = case addr of High -> d; Low -> r1
57 alu :: AluOp -> Word -> Word -> Word
59 --alu High a b = a `hwand` b
60 --alu Low a b = a `hwor` b
64 type ExecState = (RegisterBankState, Word, Word)
65 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
68 exec (addr, we, op) s =
72 (reg_s', t') = register_bank (addr, we, z) reg_s
76 -- vim: set ts=8 sw=2 sts=2 expandtab: