1 module Alu (main) where
5 main = Sim.simulate exec program initial_state
6 mainIO = Sim.simulateIO exec initial_state
10 (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
11 (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
12 (Low, High, DontCare), -- r0 = z (1)
13 (High, Low, High), -- z = r1 and t (0); t = r1 (1)
14 (High, High, DontCare) -- r1 = z (0)
17 initial_state = ((Low, High), (), Low, Low)
22 type RegisterBankState = (Bit, Bit)
24 (RegAddr, Bit, Bit) -> -- (addr, we, d)
25 RegisterBankState -> -- s
26 (RegisterBankState, Bit) -- (s', o)
28 register_bank (Low, Low, _) s = -- Read r0
31 register_bank (High, Low, _) s = -- Read r1
34 register_bank (addr, High, d) s = -- Write
38 r0' = if addr == Low then d else r0
39 r1' = if addr == High then d else r1
47 alu :: (AluOp, Bit, Bit) -> AluState -> (AluState, Bit)
48 alu (High, a, b) s = ((), a `hwand` b)
49 alu (Low, a, b) s = ((), a `hwor` b)
51 type ExecState = (RegisterBankState, AluState, Bit, Bit)
52 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
55 exec (addr, Low, op) s =
58 (reg_s, alu_s, t, z) = s
59 (reg_s', t') = register_bank (addr, Low, DontCare) reg_s
60 (alu_s', z') = alu (op, t', t) alu_s
61 s' = (reg_s', alu_s', t', z')
64 exec (addr, High, op) s =
67 (reg_s, alu_s, t, z) = s
68 (reg_s', _) = register_bank (addr, High, z) reg_s
69 s' = (reg_s', alu_s, t, z)
71 -- vim: set ts=8 sw=2 sts=2 expandtab: