5 main = Sim.simulate exec program initial_state
6 mainIO = Sim.simulateIO exec initial_state
12 (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
13 (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
14 (Low, High, dontcare), -- r0 = z (1)
15 (High, Low, High), -- z = r1 and t (0); t = r1 (1)
16 (High, High, dontcare) -- r1 = z (0)
19 --initial_state = (Regs Low High, Low, Low)
20 initial_state = ((Low, High), Low, Low)
25 type RegisterBankState = (Bit, Bit)
26 --data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
29 (RegAddr, Bit, Bit) -> -- (addr, we, d)
30 RegisterBankState -> -- s
31 (RegisterBankState, Bit) -- (s', o)
33 register_bank (Low, Low, _) s = -- Read r0
37 register_bank (High, Low, _) s = -- Read r1
41 register_bank (addr, High, d) s = -- Write
46 r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
47 r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
55 alu :: AluOp -> Bit -> Bit -> Bit
56 alu High a b = a `hwand` b
57 alu Low a b = a `hwor` b
59 salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
60 salu High a b s = (s, a `hwand` b)
61 salu Low a b s = (s, a `hwor` b)
63 type ExecState = (RegisterBankState, Bit, Bit)
64 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
67 exec (addr, Low, op) s =
71 (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
76 exec (addr, High, op) s =
80 (reg_s', _) = register_bank (addr, High, z) reg_s
83 -- vim: set ts=8 sw=2 sts=2 expandtab: