3 import CLasH.HardwareTypes hiding (fst,snd)
4 import CLasH.Translator.Annotations
5 import qualified Prelude as P
10 main = Sim.simulate exec program initial_state
11 mainIO = Sim.simulateIO exec initial_state
17 (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
18 (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
19 (Low, High, dontcare), -- r0 = z (1)
20 (High, Low, High), -- z = r1 and t (0); t = r1 (1)
21 (High, High, dontcare) -- r1 = z (0)
24 --initial_state = (Regs Low High, Low, Low)
25 initial_state = State (State (0, 1), 0, 0)
27 type Word = SizedWord D4
30 type RegisterBankState = State (Word, Word)
31 --data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
35 -> Bit -- ^ Write Enable
37 -> RegisterBankState -> -- State
38 (RegisterBankState, Word) -- (State', Output)
40 register_bank addr we d (State s) =
44 o = case addr of Low -> fst s; High -> snd s
45 in (State s, o) -- Don't change state
49 r0' = case addr of Low -> d; High -> r0
50 r1' = case addr of High -> d; Low -> r1
52 in (State s', 0) -- Don't output anything useful
58 alu :: AluOp -> Word -> Word -> Word
60 --alu High a b = a `hwand` b
61 --alu Low a b = a `hwor` b
62 alu High a b = a P.+ b
65 type ExecState = State (RegisterBankState, Word, Word)
66 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
68 {-# ANN exec TopEntity #-}
70 exec (addr, we, op) (State s) =
74 (reg_s', t') = register_bank addr we z reg_s
78 -- vim: set ts=8 sw=2 sts=2 expandtab: