From: Christiaan Baaij Date: Mon, 31 Aug 2009 18:30:04 +0000 (+0200) Subject: Added images X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=commitdiff_plain;h=d514bd151f4bd5bbb5ae6828902a778222de9738 Added images --- diff --git a/Makefile b/Makefile index b03942e..84b4934 100644 --- a/Makefile +++ b/Makefile @@ -19,8 +19,9 @@ TEXSRCS = \ preamble.tex SVGFIGURES = \ - mealymachine.svg \ mealymachine2.svg \ + mealymachine2-func-red.svg \ + mealymachine2-state-red.svg \ simpleCPU.svg \ reducer.svg diff --git a/PolyAlu.hs b/PolyAlu.hs index 8752f95..a464ffb 100644 --- a/PolyAlu.hs +++ b/PolyAlu.hs @@ -2,65 +2,57 @@ {-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-} module Main where -import qualified Prelude as P -{-# LINE 34 "PolyAlu.lhs" #-} import CLasH.HardwareTypes -{-# LINE 41 "PolyAlu.lhs" #-} import CLasH.Translator.Annotations -{-# LINE 56 "PolyAlu.lhs" #-} -type Op s a = a -> Vector s a -> a +import qualified Prelude as P +{-# LINE 51 "PolyAlu.lhs" #-} +type Op a = a -> a -> a +{-# LINE 58 "PolyAlu.lhs" #-} +type RegBank s a = + Vector (s :+: D1) a +type RegState s a = + State (RegBank s a) +{-# LINE 66 "PolyAlu.lhs" #-} +type Word = SizedInt D12 +{-# LINE 85 "PolyAlu.lhs" #-} type Opcode = Bit -{-# LINE 64 "PolyAlu.lhs" #-} -type RegBank s a = Vector (s :+: D1) a -type RegState s a = State (RegBank s a) -{-# LINE 72 "PolyAlu.lhs" #-} -type Word = SizedInt D12 -{-# LINE 89 "PolyAlu.lhs" #-} -primOp :: (a -> a -> a) -> Op s a -primOp f a b = a `f` a -{-# LINE 97 "PolyAlu.lhs" #-} -vectOp :: (a -> a -> a) -> Op s a -vectOp f a b = foldl f a b -{-# LINE 116 "PolyAlu.lhs" #-} alu :: - Op s a -> - Op s a -> - Opcode -> a -> Vector s a -> a + Op a -> Op a -> + Opcode -> a -> a -> a alu op1 op2 Low a b = op1 a b alu op1 op2 High a b = op2 a b -{-# LINE 139 "PolyAlu.lhs" #-} -registerBank :: - ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s -> - RangedWord s -> Bit -> ((RegState s a), a ) - -registerBank (State mem) data_in rdaddr wraddr wrenable = +{-# LINE 108 "PolyAlu.lhs" #-} +registers :: + ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s -> + RangedWord s -> (RegState s a) -> (RegState s a, a ) +{-# LINE 116 "PolyAlu.lhs" #-} +registers data_in rdaddr wraddr (State mem) = ((State mem'), data_out) where - data_out = mem!rdaddr - mem' | wrenable == Low = mem - | otherwise = replace mem wraddr data_in -{-# LINE 167 "PolyAlu.lhs" #-} -{-# ANN actual_cpu TopEntity#-} -actual_cpu :: - (Opcode, Word, Vector D4 Word, RangedWord D9, - RangedWord D9, Bit) -> RegState D9 Word -> - (RegState D9 Word, Word) + data_out = mem!rdaddr + mem' = replace mem wraddr data_in +{-# LINE 138 "PolyAlu.lhs" #-} +type Instruction = (Opcode, Word, RangedWord D9, RangedWord D9) +{-# LINE 142 "PolyAlu.lhs" #-} +{-# ANN cpu TopEntity#-} +cpu :: + Instruction -> RegState D9 Word -> (RegState D9 Word, Word) -actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out) +cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out) where - alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b - (ram',ram_out) = registerBank ram a rdaddr wraddr wren -{-# LINE 191 "PolyAlu.lhs" #-} + alu_out = alu (+) (-) opc d ram_out + (ram',ram_out) = registers alu_out rdaddr wraddr ram +{-# LINE 165 "PolyAlu.lhs" #-} {-# ANN initstate InitState#-} initstate :: RegState D9 Word initstate = State (copy (0 :: Word)) {-# ANN program TestInput#-} -program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)] +program :: [Instruction] program = - [ (Low, 4, copy (0), 0, 0, High) -- Write 4 to Reg0, out = 0 - , (Low, 3, copy (0), 0, 1, High) -- Write 3 to Reg1, out = 8 - , (High,0, copy (3), 1, 0, Low) -- No Write , out = 15 + [ (Low, 4, 0, 0) -- Write 4 to Reg0 + , (Low, 3, 0, 1) -- Write 3+4 to Reg1 + , (High,8, 1, 2) -- Write 8-7 to Reg2 ] run func state [] = [] @@ -73,6 +65,6 @@ main :: IO () main = do let input = program let istate = initstate - let output = run actual_cpu istate input + let output = run cpu istate input mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output return () diff --git a/PolyAlu.lhs b/PolyAlu.lhs index 547f095..c0d196d 100644 --- a/PolyAlu.lhs +++ b/PolyAlu.lhs @@ -4,6 +4,8 @@ {-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-} module Main where +import CLasH.HardwareTypes +import CLasH.Translator.Annotations import qualified Prelude as P \end{code} %endif @@ -12,12 +14,18 @@ import qualified Prelude as P \subsection{Introduction} \frame { -\frametitle{Small Use Case}\pause -TODO: Plaatje +\frametitle{Small Use Case} +\begin{columns}[l] +\column{0.5\textwidth} +\begin{figure} +\includegraphics[width=4.75cm]{simpleCPU} +\end{figure} +\column{0.5\textwidth} \begin{itemize} - \item Polymorphic, Higher-Order CPU\pause + \item Polymorphic, Higher-Order CPU \item Use of state will be simple \end{itemize} +\end{columns} }\note[itemize]{ \item Small "toy"-example of what can be done in \clash{} \item Show what can be translated to Hardware @@ -29,21 +37,36 @@ TODO: Plaatje \frame { \frametitle{Type definitions}\pause -TODO: Plaatje van de ALU +\begin{columns}[l] +\column{0.5\textwidth} +\begin{figure} +\includegraphics[width=4.75cm]{simpleCPU} +\end{figure} +\column{0.5\textwidth} +\vspace{2em} + First we define some ALU types: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} type Op a = a -> a -> a \end{code} \end{beamercolorbox}\pause - +\vspace{2.5em} And some Register types: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} -type RegBank s a = Vector (s :+: D1) a -type RegState s a = State (RegBank s a) +type RegBank s a = + Vector (s :+: D1) a +type RegState s a = + State (RegBank s a) \end{code} -\end{beamercolorbox}\pause +\end{beamercolorbox} +%if style == newcode +\begin{code} +type Word = SizedInt D12 +\end{code} +%endif +\end{columns} }\note[itemize]{ \item The first type is already polymorphic in input / output type \item State has to be of the State type to be recognized as such @@ -53,6 +76,9 @@ type RegState s a = State (RegBank s a) \frame { \frametitle{Simple ALU} +\begin{figure} +\includegraphics[width=5.25cm,trim=0mm 5.5cm 0mm 1cm, clip=true]{simpleCPU} +\end{figure} Abstract ALU definition: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} @@ -64,9 +90,6 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-} a b = op1 a b alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \end{code} \end{beamercolorbox} -\begin{itemize} -\uncover<2->{\item We support Pattern Matching} -\end{itemize} }\note[itemize]{ \item Alu is both higher-order, and polymorphic \item Two parameters are "compile time", others are "runtime" @@ -77,24 +100,26 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \frame { \frametitle{Register Bank} -Make a simple register bank: -\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -TODO: Hide type sig +\begin{figure} +\includegraphics[width=5.25cm,trim=0mm 0.4cm 0mm 6.2cm, clip=true]{simpleCPU} +\end{figure} +%if style == newcode \begin{code} -registerBank :: +registers :: CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s -> - RangedWord s -> Bool -> (RegState s a) -> ((RegState s a), a ) - -registerBank data_in rdaddr wraddr (State mem) = + RangedWord s -> (RegState s a) -> (RegState s a, a ) +\end{code} +%endif +A simple register bank: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} +\begin{code} +registers data_in rdaddr wraddr (State mem) = ((State mem'), data_out) where data_out = mem!rdaddr mem' = replace mem wraddr data_in \end{code} \end{beamercolorbox} -\begin{itemize} -\uncover<2->{\item We support Guards} -\end{itemize} }\note[itemize]{ \item RangedWord runs from 0 to the upper bound \item mem is statefull @@ -108,21 +133,25 @@ registerBank data_in rdaddr wraddr (State mem) = \frametitle{Simple CPU} Combining ALU and register bank: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -TODO: Hide Instruction type? +%if style == newcode +\begin{code} +type Instruction = (Opcode, Word, RangedWord D9, RangedWord D9) +\end{code} +%endif \begin{code} -type Instruction = (Opcode, Word, RangedWord D9, RangedWord D9) -> RegState D9 Word -> -{-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-} -actual_cpu :: +{-"{\color<2>[rgb]{1,0,0}"-}ANN(cpu TopEntity){-"}"-} +cpu :: Instruction -> RegState D9 Word -> (RegState D9 Word, Word) -actual_cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out) +cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out) where - alu_out = alu ({-"{\color<3>[rgb]{1,0,0}"-}(+){-"}"-}) ({-"{\color<3>[rgb]{1,0,0}"-}(-){-"}"-}) opc d ram_out - (ram',ram_out) = registerBank alu_out rdaddr wraddr ram + alu_out = alu {-"{\color<3>[rgb]{1,0,0}"-}(+){-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}(-){-"}"-} opc d ram_out + (ram',ram_out) = registers alu_out rdaddr wraddr ram \end{code} \end{beamercolorbox} \begin{itemize} \uncover<2->{\item Annotation is used to indicate top-level component} +\uncover<3->{\item Instantiate actual operations} \end{itemize} }\note[itemize]{ \item We use the new Annotion functionality to indicate this is the top level. TopEntity is defined by us. @@ -138,11 +167,11 @@ initstate :: RegState D9 Word initstate = State (copy (0 :: Word)) ANN(program TestInput) -program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)] +program :: [Instruction] program = - [ (Low, 4, copy (0), 0, 0, High) -- Write 4 to Reg0, out = 0 - , (Low, 3, copy (0), 0, 1, High) -- Write 3 to Reg1, out = 8 - , (High,0, copy (3), 1, 0, Low) -- No Write , out = 15 + [ (Low, 4, 0, 0) -- Write 4 to Reg0 + , (Low, 3, 0, 1) -- Write 3+4 to Reg1 + , (High,8, 1, 2) -- Write 8-7 to Reg2 ] run func state [] = [] @@ -155,7 +184,7 @@ main :: IO () main = do let input = program let istate = initstate - let output = run actual_cpu istate input + let output = run cpu istate input mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output return () \end{code} diff --git a/beamerinnerthemecaes.sty b/beamerinnerthemecaes.sty index 664af83..580fe3c 100644 --- a/beamerinnerthemecaes.sty +++ b/beamerinnerthemecaes.sty @@ -29,6 +29,34 @@ \makeatletter +% +% +% The \committee command +% +% +\def\committee{\@dblarg\beamer@committee} +\long\def\beamer@committee[#1]#2{% + \def\beamer@temp{#2}% + \ifx\beamer@temp\@empty + \def\insertcommittee{} + \else + \def\insertcommittee{\def\inst{\beamer@committee}\def\and{\beamer@andcommittee}#2}% + \fi + \def\beamer@shortcommittee{#1}} +\committee{} + +\def\beamer@instcommittee#1{{\donotcoloroutermaths$^{#1}$}\ignorespaces} +\def\beamer@andcommittee{\\[1em]} + +\newcommand\insertshortcommittee[1][]{% + {% + \let\thanks=\@gobble% + \def\inst{\beamer@committeeother}\def\and{\beamer@andcommittee}% + \beamer@setupshort{#1}% + \beamer@insertshort{\beamer@shortcommittee}% + }} + + \setbeamertemplate{title page} { \begin{centering} @@ -51,7 +79,7 @@ \end{beamercolorbox} \fi \begin{beamercolorbox}[sep=4pt,center]{date} - \usebeamerfont{date}\insertdate + \usebeamerfont{date}\insertcommittee \end{beamercolorbox} % {\usebeamercolor[fg]{titlegraphic}\inserttitlegraphic\par} \vfill diff --git a/clash-haskell09.lhs b/clash-haskell09.lhs index 3f28819..ad01d4e 100644 --- a/clash-haskell09.lhs +++ b/clash-haskell09.lhs @@ -6,7 +6,7 @@ \title{\clash{}} \subtitle{From Haskell To Hardware} \author{Christiaan Baaij \& Matthijs Kooijman} -\author{Supervisor: Jan Kuper} +\committee{Supervisor: Jan Kuper} \date{September 3, 2009} \begin{document} diff --git a/cpualu.png b/cpualu.png new file mode 100644 index 0000000..ed1baee Binary files /dev/null and b/cpualu.png differ diff --git a/cpucomplete.png b/cpucomplete.png new file mode 100644 index 0000000..dd138b2 Binary files /dev/null and b/cpucomplete.png differ diff --git a/cpuregisters.png b/cpuregisters.png new file mode 100644 index 0000000..977afb6 Binary files /dev/null and b/cpuregisters.png differ diff --git a/demo.lhs b/demo.lhs index 0399cc8..61a5567 100644 --- a/demo.lhs +++ b/demo.lhs @@ -3,15 +3,23 @@ \frame{ \frametitle{Demo} \begin{itemize} - \item We will simulate the small CPU - \item Translate that CPU code to VHDL + \item Simulate the CPU description + \item Translate the CPU to VHDL \item Simulate the generated VHDL - \item See the hardware schematic of the synthesized VHDL \end{itemize} }\note[itemize]{ \item Will show video } +\frame{ +\frametitle{Generated Schematic} +\begin{figure} +\centerline{\includegraphics<1>[width=10cm]{cpucomplete} +\includegraphics<2>[width=10cm]{cpualu} +\includegraphics<3>[height=6cm]{cpuregisters}} +\end{figure} +} + % % \frame{ % \frametitle{How do we use \clash{}?} diff --git a/introduction.lhs b/introduction.lhs index e0a72ff..c7b0bca 100644 --- a/introduction.lhs +++ b/introduction.lhs @@ -15,70 +15,65 @@ { \item We are a Computer Architectures group, this has been a Masters' project, no prior experience with Haskell. \item \clash{} is written in Haskell, of course -\item \clash{} is currently meant for rapid prototyping, not verification of hardware desigs +\item \clash{} is currently meant for rapid prototyping, not verification of hardware designs \item Functional languages are close to Hardware \item We can only translate a subset of Haskell \item All functions are descriptions of Mealy Machines } -\subsection{Mealy Machine} -\frame -{ -\frametitle{What is a Mealy Machine again?} - \begin{figure} - \centerline{\includegraphics[width=10cm]{mealymachine}} - \label{img:mealymachine} - \end{figure} -} -\note[itemize]{ -\item Mealy machine bases its output on current input and previous state -\item: TODO: Integrate this slide with the next two. First, show the picture -with the mealyMachine type signature (and rename it to "func"). Then, show the -run function, without type signature. Focus is on correspondence to the -picture. -} +% \subsection{Mealy Machine} +% \frame +% { +% \frametitle{What is a Mealy Machine again?} +% \begin{figure} +% \centerline{\includegraphics[width=10cm]{mealymachine}} +% \label{img:mealymachine} +% \end{figure} +% } +% \note[itemize]{ +% \item Mealy machine bases its output on current input and previous state +% \item: TODO: Integrate this slide with the next two. First, show the picture +% with the mealyMachine type signature (and rename it to "func"). Then, show the +% run function, without type signature. Focus is on correspondence to the +% picture. +% } \frame { \frametitle{Haskell Description} +\begin{figure} +\centerline{\includegraphics<1>[width=6.25cm]{mealymachine2} +\includegraphics<2>[width=6.25cm]{mealymachine2-func-red} +\includegraphics<3>[width=6.25cm]{mealymachine2-state-red}} +\label{img:mealymachine} +\end{figure} \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} -mealyMachine :: - InputSignals -> - {-"{\color<2>[rgb]{1,0,0}"-}State{-"}"-} -> - (State, OutputSignals) +run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} [] = [] +run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs + where + ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} i {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} + outputs = run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input \end{code} \end{beamercolorbox} -\begin{itemize} -\uncover<2->{\item Current state is part of the input} -\uncover<3->{\item New state is part of the output} -\end{itemize} } \note[itemize]{ \item State is part of the function signature \item Both the current state, as the updated State } -\subsection{Simulation} \frame { -\frametitle{Simulating a Mealy Machine} +\frametitle{Haskell Description} +\begin{figure} +\centerline{\includegraphics[width=6.25cm]{mealymachine2-func-red}} +\end{figure} \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} -run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} [] = [] -run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out - where - ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = func i {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} - out = run func {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input +func :: + InputSignal -> + State -> + (State, OutputSignal) \end{code} \end{beamercolorbox} -\begin{itemize} -\item State behaves like an accumulator -\item Input is a (normal) list of inputs, one for each cycle -\end{itemize} } -\note[itemize]{ -\item This is just a quick example of how we can simulate the mealy machine -\item It sort of behaves like MapAccumN -} - diff --git a/mealymachine2-func-red.svg b/mealymachine2-func-red.svg new file mode 100644 index 0000000..21a7d1b --- /dev/null +++ b/mealymachine2-func-red.svg @@ -0,0 +1,229 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + func + + + state + + (i : inputs) + (o : outputs) + diff --git a/mealymachine2-state-red.svg b/mealymachine2-state-red.svg new file mode 100644 index 0000000..0754f35 --- /dev/null +++ b/mealymachine2-state-red.svg @@ -0,0 +1,225 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + func + + state + (i : inputs) + (o : outputs) + diff --git a/mealymachine2.svg b/mealymachine2.svg new file mode 100644 index 0000000..251780c --- /dev/null +++ b/mealymachine2.svg @@ -0,0 +1,229 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + func + + + state + + (i : inputs) + (o : outputs) + diff --git a/polyaluhardware-add.png b/polyaluhardware-add.png deleted file mode 100644 index 83e4c65..0000000 Binary files a/polyaluhardware-add.png and /dev/null differ diff --git a/polyaluhardware-reg.png b/polyaluhardware-reg.png deleted file mode 100644 index 6a49453..0000000 Binary files a/polyaluhardware-reg.png and /dev/null differ diff --git a/polyaluhardware.png b/polyaluhardware.png deleted file mode 100644 index 5a35f06..0000000 Binary files a/polyaluhardware.png and /dev/null differ diff --git a/reducer.lhs b/reducer.lhs index 4d74c68..03c688c 100644 --- a/reducer.lhs +++ b/reducer.lhs @@ -2,13 +2,19 @@ \frame{ \frametitle{More than just toys} \pause -TODO: Plaatje van de reducer +\begin{columns}[l] +\column{0.5\textwidth} +\begin{figure} +\includegraphics<2->[width=5.5cm]{reducer} +\end{figure} +\column{0.5\textwidth} \begin{itemize} \item We implemented a reduction circuit in \clash{}\pause \item Simulation results in Haskell match VHDL simulation results\pause \item Synthesis completes without errors or warnings\pause - \item Around half speed of handcoded and optimized VHDL \pause + \item Around half speed of handcoded and optimized VHDL \end{itemize} +\end{columns} }\note[itemize]{ \item Toys like the poly cpu one are good to give a quick demo \item But we used \clash{} to design 'real' hardware @@ -16,8 +22,8 @@ TODO: Plaatje van de reducer \item Nice speed considering we don't optimize for it (only single example!) } -\begin{frame}[plain] - \begin{centering} - \includegraphics[height=\paperheight]{reducerschematic.png} - \end{centering} -\end{frame} +% \begin{frame}[plain] +% \begin{centering} +% \includegraphics[height=\paperheight]{reducerschematic.png} +% \end{centering} +% \end{frame} diff --git a/reducer.svg b/reducer.svg new file mode 100644 index 0000000..39152bc --- /dev/null +++ b/reducer.svg @@ -0,0 +1,379 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/reducerschematic.png b/reducerschematic.png deleted file mode 100644 index 0d5f0a2..0000000 Binary files a/reducerschematic.png and /dev/null differ diff --git a/simpleCPU.svg b/simpleCPU.svg new file mode 100644 index 0000000..d24d179 --- /dev/null +++ b/simpleCPU.svg @@ -0,0 +1,411 @@ + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ALU + Registers + + + + CPU + + + opc + a + b + data_in + rdaddr + + wraddr + data_out + alu_out + diff --git a/summary.lhs b/summary.lhs index 94b11b5..58feaa9 100644 --- a/summary.lhs +++ b/summary.lhs @@ -22,34 +22,18 @@ \frame { -\frametitle{Complete signature for registerBank} +\frametitle{Complete signatures and Types} \begin{code} -registerBank :: - ( NaturalT s +type Word = SizedInt D12 +type Instruction = ( Opcode, Word, RangedWord D9 + , RangedWord D9 ) + +registers :: + ( NaturalT s , PositiveT (s :+: D1) - , ((s :+: D1) :>: s) ~ True )) => - (RegState s a) -> a -> RangedWord s -> - RangedWord s -> Bit -> ((RegState s a), a ) + , ((s :+: D1) :>: s) ~ True )) => + a -> RangedWord s -> RangedWord s -> + (RegState s a) -> + (RegState s a, a ) \end{code} } - -\frame{ -\begin{figure} -\centerline{\includegraphics[width=12cm]{polyaluhardware}} -\label{img:mealymachine} -\end{figure} -} - -\frame{ -\begin{figure} -\centerline{\includegraphics[width=12cm]{polyaluhardware-reg}} -\label{img:mealymachine} -\end{figure} -} - -\frame{ -\begin{figure} -\centerline{\includegraphics[width=12cm]{polyaluhardware-add}} -\label{img:mealymachine} -\end{figure} -}