import CLasH.HardwareTypes hiding (min,foldl1,const)
import CLasH.Translator.Annotations
-type Word = SizedInt D16
-type Index = RangedWord
+type CpuState = State (Vector D4 (Signed D16))
-const a b = a
+fu op inputs (a1, a2) =
+ op (inputs!a1) (inputs!a2)
-fu op inputs (addr1, addr2) = regIn
- where
- in1 = inputs!addr1
- in2 = inputs!addr2
- regIn = op in1 in2
+fu1 = fu (+)
+fu2 = fu (-)
+fu3 = fu (*)
+
+data Opcode = Shift | Xor | Equal
-type CpuState = State (Vector D4 Word)
+multiop Shift = shift
+multiop Xor = xor
+multiop Equal = \a b -> if a == b then 1 else 0
+
+fu0 c = fu (multiop c)
{-# ANN cpu TopEntity #-}
{-# ANN cpu (InitState 'cpuState) #-}
-cpu :: CpuState -> Word -> Vector D4 (Index D6, Index D6) -> Opcode
- -> (CpuState, Word)
-cpu (State fuss) input addrs opc = (State fuss', out)
+cpu :: CpuState
+ -> (Signed D16, Opcode, Vector D4 (Index D6, Index D6))
+ -> (CpuState, Signed D16)
+cpu (State s) (x,opc,addrs) = (State s', out)
where
- fuss' = (fu (multiop opc) inputs (addrs!(0 :: Index D3))) +> (
- (fu (+) inputs (addrs!(1 :: Index D3))) +> (
- (fu (-) inputs (addrs!(2 :: Index D3))) +> (
- (fu (*) inputs (addrs!(3 :: Index D3))) +> empty)))
- inputs = 0 +> (1 +> (input +> fuss))
- out = head fuss
-
-cpuState :: Vector D4 Word
+ inputs = x +> (0 +> (1 +> s))
+ s' = (fu0 opc inputs (addrs!(0 :: Index D3))) +> (
+ (fu1 inputs (addrs!(1 :: Index D3))) +> (
+ (fu2 inputs (addrs!(2 :: Index D3))) +> (
+ (fu3 inputs (addrs!(3 :: Index D3))) +> empty)))
+ out = last s
+
+-- Some minor details
+cpuState :: Vector D4 (Signed D16)
cpuState = copy 0
-data Opcode = Shift | Xor | Equal
-
-multiop :: Opcode -> Word -> Word -> Word
-multiop opc a b = case opc of
- Shift -> shift a b
- Xor -> xor a b
- Equal | a == b -> 1
- | otherwise -> 0
+type Index = RangedWord
+type Signed = SizedInt
--- Placeholders, since we don't have these operations
+const a b = a
xor = const
shift = const