Always rotate alternatives of case-statements. Original bug was caused by reverse...
authorchristiaanb <christiaan.baaij@gmail.com>
Thu, 24 Jun 2010 09:34:01 +0000 (11:34 +0200)
committerchristiaanb <christiaan.baaij@gmail.com>
Thu, 24 Jun 2010 09:34:01 +0000 (11:34 +0200)
commit70654a9d134697f4d3703ff4a8747a1e078afd7b
treee7c6e0fe92b3b82f4b8e387daa2810d64fcff757
parentce377516c0de6e03b6b72a870b2020eecee09e77
Always rotate alternatives of case-statements. Original bug was caused by reverse order of true and false vhdl literals
clash/CLasH/VHDL/Generate.hs