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Make top level inlining handle non-representable results gracefully.
[matthijs/master-project/cλash.git]
/
reducer.hs
2010-03-31
christiaanb
Update reducer to latest design (that runs at 159 MHz)
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2009-11-10
Christiaan Baaij
Fixed VHDL Type generation, vhdlTy now uses HType's...
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2009-11-06
Christiaan Baaij
Update reducer
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2009-08-20
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-08-19
Matthijs Kooijman
Merge branch 'master' of git://github.com/christiaanb...
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2009-08-18
Christiaan Baaij
Work around some bugs in the current clash to make...
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2009-08-14
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-08-14
Christiaan Baaij
Add builtin blockRAM primitive
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2009-08-14
Matthijs Kooijman
Merge branch 'master' of git://github.com/christiaanb...
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2009-08-14
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-08-13
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-08-13
Christiaan Baaij
Generate more unique variable names, generate truely...
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2009-08-13
Christiaan Baaij
Add boolean or and and, tuple fst and snd function.
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