From: Matthijs Kooijman Date: Thu, 29 Jan 2009 10:36:34 +0000 (+0100) Subject: Add some comments. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=844555bd28c13cfe1bcb450960008e81928fe2c5;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Add some comments. --- diff --git a/Adders.hs b/Adders.hs index c398578..f29927c 100644 --- a/Adders.hs +++ b/Adders.hs @@ -10,18 +10,18 @@ show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displ b = [Low, Low, Low, High] (s, c) = f (a, b) --- Combinatoric no-carry adder +-- Combinatoric stateless no-carry adder -- A -> B -> S no_carry_adder :: (Bit, Bit) -> Bit no_carry_adder (a, b) = a `hwxor` b --- Combinatoric half adder +-- Combinatoric stateless half adder -- A -> B -> (S, C) half_adder :: (Bit, Bit) -> (Bit, Bit) half_adder (a, b) = ( a `hwxor` b, a `hwand` b ) --- Combinatoric (one-bit) full adder +-- Combinatoric stateless full adder -- (A, B, C) -> (S, C) full_adder :: (Bit, Bit, Bit) -> (Bit, Bit) full_adder (a, b, cin) = (s, c) diff --git a/Alu.hs b/Alu.hs index 2495df2..59e5fd5 100644 --- a/Alu.hs +++ b/Alu.hs @@ -16,8 +16,7 @@ program = [ initial_state = ((Low, High), (), Low, Low) --- --- +-- Register bank type RegAddr = Bit type RegisterBankState = (Bit, Bit) @@ -40,6 +39,8 @@ register_bank (addr, High, d) s = -- Write r1' = if addr == High then d else r1 s' = (r0', r1') +-- ALU + type AluState = () type AluOp = Bit