From: Matthijs Kooijman Date: Tue, 14 Apr 2009 09:51:58 +0000 (+0200) Subject: Let VHDL generate a typecast for SizedWord literals. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=6f6ac4641e210ded85e42fdcceb316bd0ed64d13;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Let VHDL generate a typecast for SizedWord literals. --- diff --git a/Flatten.hs b/Flatten.hs index 30a9bba..74b3232 100644 --- a/Flatten.hs +++ b/Flatten.hs @@ -218,9 +218,12 @@ flattenExpr binds app@(App _ _) = do sig_id <- genSignalId SigInternal ty -- TODO: fromInteger is defined for more types than just SizedWord let len = sized_word_len ty - -- TODO: to_stdlogicvector doesn't work here, since SizedWord - -- translates to a different type... - addDef $ UncondDef (Right $ Literal ("to_stdlogicvector(to_unsigned(" ++ (show int) ++ ", " ++ (show len) ++ "))") Nothing) sig_id + -- Use a to_unsigned to translate the number (a natural) to an unsiged + -- (array of bits) + let lit_str = "to_unsigned(" ++ (show int) ++ ", " ++ (show len) ++ ")" + -- Set the signal to our literal unconditionally, but add the type so + -- the literal will be typecast to the proper type. + addDef $ UncondDef (Right $ Literal lit_str (Just ty)) sig_id return ([], Single sig_id) else flattenApplicationExpr binds (CoreUtils.exprType app) f args