From: Matthijs Kooijman Date: Tue, 14 Apr 2009 09:24:34 +0000 (+0200) Subject: Add a Type to a Literal SignalExpr. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=6e1beb07825c53ab0da16b815d58c24a1b4ea449;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Add a Type to a Literal SignalExpr. The Type is still unused, but will be used for making the VHDL backend add a typecast (since the actual VHDL name for the type is not known earlier). --- diff --git a/Flatten.hs b/Flatten.hs index e434f2e..30a9bba 100644 --- a/Flatten.hs +++ b/Flatten.hs @@ -169,7 +169,7 @@ flattenExpr binds var@(Var id) = sig_id <- genSignalId SigInternal ty -- Add a name hint to the signal addNameHint (Name.getOccString id) sig_id - addDef (UncondDef (Right $ Literal lit) sig_id) + addDef (UncondDef (Right $ Literal lit Nothing) sig_id) return ([], Single sig_id) IdInfo.VanillaGlobal -> -- Treat references to globals as an application with zero elements @@ -220,7 +220,7 @@ flattenExpr binds app@(App _ _) = do let len = sized_word_len ty -- TODO: to_stdlogicvector doesn't work here, since SizedWord -- translates to a different type... - addDef (UncondDef (Right $ Literal $ "to_stdlogicvector(to_unsigned(" ++ (show int) ++ ", " ++ (show len) ++ "))") sig_id) + addDef $ UncondDef (Right $ Literal ("to_stdlogicvector(to_unsigned(" ++ (show int) ++ ", " ++ (show len) ++ "))") Nothing) sig_id return ([], Single sig_id) else flattenApplicationExpr binds (CoreUtils.exprType app) f args diff --git a/FlattenTypes.hs b/FlattenTypes.hs index f20fbc3..bd6c1d5 100644 --- a/FlattenTypes.hs +++ b/FlattenTypes.hs @@ -113,14 +113,18 @@ sigDefUses (FApp _ args _) = concat $ map Foldable.toList args -- | An expression on signals data SignalExpr = EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal - | Literal String -- ^ A literal value + | Literal String (Maybe Type.Type)-- ^ A literal value, with an optional type to cast to | Eq SignalId SignalId -- ^ A comparison between to signals deriving (Show, Eq) +-- Instantiate Eq for Type, so we can derive Eq for SignalExpr. +instance Eq Type.Type where + (==) = Type.coreEqType + -- | Which signals are used by the given SignalExpr? sigExprUses :: SignalExpr -> [SignalId] sigExprUses (EqLit id _) = [id] -sigExprUses (Literal _) = [] +sigExprUses (Literal _ _) = [] sigExprUses (Eq a b) = [a, b] -- Returns the function used by the given SigDef, if any diff --git a/Pretty.hs b/Pretty.hs index ef92c4d..0cc2b59 100644 --- a/Pretty.hs +++ b/Pretty.hs @@ -76,8 +76,8 @@ instance Pretty SigDef where instance Pretty SignalExpr where pPrint (EqLit id lit) = parens $ pPrint id <> text " = " <> text lit - pPrint (Literal lit) = - text lit + pPrint (Literal lit ty) = + text "(" <> text (show ty) <> text ") " <> text lit pPrint (Eq a b) = parens $ pPrint a <> text " = " <> pPrint b diff --git a/VHDL.hs b/VHDL.hs index 67ef0c7..0803419 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -275,7 +275,7 @@ mkConcSm _ sigs (UncondDef src dst) _ = case expr of (EqLit id lit) -> (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit) - (Literal lit) -> + (Literal lit _) -> AST.PrimLit lit (Eq a b) -> (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)