From: Matthijs Kooijman Date: Tue, 17 Feb 2009 14:49:24 +0000 (+0100) Subject: Add clk port on any stateful entity. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=157dae90bdd7c45613c6ad6185383a1137b2323f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Add clk port on any stateful entity. --- diff --git a/FlattenTypes.hs b/FlattenTypes.hs index 5c95632..e7d21d6 100644 --- a/FlattenTypes.hs +++ b/FlattenTypes.hs @@ -1,6 +1,7 @@ module FlattenTypes where import Data.Traversable +import qualified Data.Foldable as Foldable import qualified Control.Monad.State as State import CoreSyn @@ -28,6 +29,11 @@ data HsValueUse = } deriving (Show, Eq, Ord) +-- | Is this HsValueUse a state use? +isStateUse :: HsValueUse -> Bool +isStateUse (State _) = True +isStateUse _ = False + -- | A map from a Haskell value to the use of each single value type HsUseMap = HsValueMap HsValueUse @@ -60,6 +66,11 @@ data HsFunction = HsFunction { hsFuncRes :: HsUseMap } deriving (Show, Eq, Ord) +hasState :: HsFunction -> Bool +hasState hsfunc = + any (Foldable.any isStateUse) (hsFuncArgs hsfunc) + || Foldable.any isStateUse (hsFuncRes hsfunc) + -- | A flattened function application data FApp sigid = FApp { appFunc :: HsFunction, diff --git a/VHDL.hs b/VHDL.hs index ef89c4a..ee61c50 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -58,7 +58,7 @@ createEntity hsfunc fdata = (sigName info) ty = sigTy info --- | Create the VHDL AST for an entity + -- | Create the VHDL AST for an entity createEntityAST :: HsFunction -- | The signature of the function we're working with -> [VHDLSignalMap] -- | The entity's arguments @@ -71,9 +71,16 @@ createEntityAST hsfunc args res = vhdl_id = mkEntityId hsfunc ports = concatMap (mapToPorts AST.In) args ++ mapToPorts AST.Out res + ++ clk_port mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] mapToPorts mode m = map (mkIfaceSigDec mode) (Foldable.toList m) + -- Add a clk port if we have state + clk_port = if hasState hsfunc + then + [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty] + else + [] -- | Create a port declaration mkIfaceSigDec :: @@ -230,6 +237,10 @@ getLibraryUnits (hsfunc, fdata) = bit_ty :: AST.TypeMark bit_ty = AST.unsafeVHDLBasicId "Bit" +-- | The VHDL std_logic +std_logic_ty :: AST.TypeMark +std_logic_ty = AST.unsafeVHDLBasicId "std_logic" + -- Translate a Haskell type to a VHDL type vhdl_ty :: Type.Type -> AST.TypeMark vhdl_ty ty = Maybe.fromMaybe