From: Christiaan Baaij Date: Mon, 29 Jun 2009 08:11:48 +0000 (+0200) Subject: Added "zip" function X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=1476a5bd6c7c174ffbd39a178caa9701bdd39ac1;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Added "zip" function --- diff --git a/Adders.hs b/Adders.hs index 408e6b8..b17f744 100644 --- a/Adders.hs +++ b/Adders.hs @@ -174,8 +174,8 @@ highordtest = \x -> xand a b = hwand a b -functiontest :: TFVec D4 Bit -> TFVec D2 Bit -functiontest = \v -> let r = select d0 d1 d2 v in r +functiontest :: TFVec D4 Bit -> TFVec D4 Bit -> TFVec D4 (Bit, Bit) +functiontest = \v1 v2 -> let r = zip v1 v2 in r xhwnot x = hwnot x diff --git a/Constants.hs b/Constants.hs index 380a745..60aba4e 100644 --- a/Constants.hs +++ b/Constants.hs @@ -165,12 +165,18 @@ mapId = "map" zipWithId :: String zipWithId = "zipWith" +-- | foldl function identifier foldlId :: String foldlId = "foldl" +-- | foldr function identifier foldrId :: String foldrId = "foldr" +-- | zip function identifier +zipId :: String +zipId = "zip" + -- | hwxor function identifier hwxorId :: String hwxorId = "hwxor" diff --git a/Generate.hs b/Generate.hs index 75ee1d3..691a27d 100644 --- a/Generate.hs +++ b/Generate.hs @@ -222,6 +222,32 @@ genFold' left (Left res) f [folded_f, start, vec] = do -- Return the conditional generate part return $ AST.GenerateSm cond_label cond_scheme [] app_concsms +-- | Generate a generate statement for the builtin function "zip" +genZip :: BuiltinBuilder +genZip = genVarArgs genZip' +genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm] +genZip' (Left res) f args@[arg1, arg2] = + let + -- Setup the generate scheme + len = (tfvec_len . Var.varType) res + -- TODO: Use something better than varToString + label = mkVHDLExtId ("zipVector" ++ (varToString res)) + n_id = mkVHDLBasicId "n" + n_expr = idToVHDLExpr n_id + range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) + genScheme = AST.ForGn n_id range + resname' = mkIndexedName (varToVHDLName res) n_expr + argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr + argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr + in do + labels <- getFieldLabels (tfvec_elem (Var.varType res)) + let resnameA = mkSelectedName resname' (labels!!0) + let resnameB = mkSelectedName resname' (labels!!1) + let resA_assign = mkUncondAssign (Right resnameA) argexpr1 + let resB_assign = mkUncondAssign (Right resnameB) argexpr2 + -- Return the generate functions + return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]] + ----------------------------------------------------------------------------- -- Function to generate VHDL for applications ----------------------------------------------------------------------------- @@ -578,6 +604,7 @@ globalNameTable = Map.fromList , (zipWithId , (3, genZipWith ) ) , (foldlId , (3, genFoldl ) ) , (foldrId , (3, genFoldr ) ) + , (zipId , (2, genZip ) ) , (emptyId , (0, genFCall ) ) , (singletonId , (1, genFCall ) ) , (copyId , (2, genFCall ) )