From: Christiaan Baaij Date: Thu, 6 Aug 2009 13:02:40 +0000 (+0200) Subject: Add the type-alias Vector for TFVec to HardwareTypes, and don't export TFVec.TFVec... X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=08b9e0c5831fc9ea188395b6e272359bf439568f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Add the type-alias Vector for TFVec to HardwareTypes, and don't export TFVec.TFVec anymore --- diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs index 39bf4d9..e5dcbfd 100644 --- a/HighOrdAlu.hs +++ b/HighOrdAlu.hs @@ -26,11 +26,11 @@ anyset f s a b = constant (f a' b') a b xhwor = hwor -type Op n e = (TFVec n e -> TFVec n e -> TFVec n e) +type Op n e = (Vector n e -> Vector n e -> Vector n e) type Opcode = Bit {-# ANN sim_input TestInput#-} -sim_input :: [(Opcode, TFVec D4 (SizedInt D8), TFVec D4 (SizedInt D8))] +sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))] sim_input = [ (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) , (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) , (Low, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) ] @@ -38,14 +38,14 @@ sim_input = [ (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3 {-# ANN actual_alu InitState #-} initstate = High -alu :: Op n e -> Op n e -> Opcode -> TFVec n e -> TFVec n e -> TFVec n e +alu :: Op n e -> Op n e -> Opcode -> Vector n e -> Vector n e -> Vector n e alu op1 op2 opc a b = case opc of Low -> op1 a b High -> op2 a b {-# ANN actual_alu TopEntity #-} -actual_alu :: (Opcode, TFVec D4 (SizedInt D8), TFVec D4 (SizedInt D8)) -> TFVec D4 (SizedInt D8) +actual_alu :: (Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8)) -> Vector D4 (SizedInt D8) --actual_alu = alu (constant Low) andop actual_alu (opc, a, b) = alu (anyset (+) (0 :: SizedInt D8)) (andop (-)) opc a b diff --git "a/c\316\273ash/CLasH/HardwareTypes.hs" "b/c\316\273ash/CLasH/HardwareTypes.hs" index b48760a..9209086 100644 --- "a/c\316\273ash/CLasH/HardwareTypes.hs" +++ "b/c\316\273ash/CLasH/HardwareTypes.hs" @@ -8,6 +8,7 @@ module CLasH.HardwareTypes , module Data.SizedWord , module Prelude , Bit(..) + , Vector , hwand , hwor , hwxor @@ -19,7 +20,8 @@ import Prelude hiding ( null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr, zipWith, zip, unzip, concat, reverse, iterate ) import Types -import Data.Param.TFVec +import qualified Data.Param.TFVec as TFVec +import Data.Param.TFVec hiding (TFVec) import Data.RangedWord import Data.SizedInt import Data.SizedWord @@ -27,6 +29,8 @@ import Data.SizedWord import Language.Haskell.TH.Lift import Data.Typeable +type Vector = TFVec.TFVec + -- The plain Bit type data Bit = High | Low deriving (P.Show, P.Eq, P.Read, Typeable)