ncline(andb)(out);
\stopuseMPgraphic
+ \startbuffer[And3VHDL]
+ entity and3Component_0 is
+ port (\azMyG2\ : in std_logic;
+ \bzMyI2\ : in std_logic;
+ \czMyK2\ : in std_logic;
+ \foozMySzMyS2\ : out std_logic;
+ clock : in std_logic;
+ resetn : in std_logic);
+ end entity and3Component_0;
+
+
+ architecture structural of and3Component_0 is
+ signal \argzMyMzMyM2\ : std_logic;
+ begin
+ \argzMyMzMyM2\ <= \azMyG2\ and \bzMyI2\;
+
+ \foozMySzMyS2\ <= \argzMyMzMyM2\ and \czMyK2\;
+ end architecture structural;
+ \stopbuffer
+
\placeexample[][ex:And3]{Simple three input and gate.}
\startcombination[2*1]
{\typebufferhs{And3}}{Haskell description using function applications.}
{\boxedgraphic{And3}}{The architecture described by the Haskell description.}
\stopcombination
+ \placeexample[][ex:And3VHDL]{\VHDL\ generated for \hs{and3} from \in{example}[ex:And3]}
+ {\typebuffervhdl{And3VHDL}}
+
\placeintermezzo{}{
\defref{top level binder}
\defref{top level function}
ncline(trueout)(mux) "posB(inpb)";
ncline(mux)(out) "posA(out)";
\stopuseMPgraphic
+
+ \startbuffer[CaseInvVHDL]
+ entity invComponent_0 is
+ port (\xzAMo2\ : in boolean;
+ \reszAMuzAMu2\ : out boolean;
+ clock : in std_logic;
+ resetn : in std_logic);
+ end entity invComponent_0;
+
+
+ architecture structural of invComponent_0 is
+ begin
+ \reszAMuzAMu2\ <= false when \xzAMo2\ = true else
+ true;
+ end architecture structural;
+ \stopbuffer
\placeexample[][ex:CaseInv]{Simple inverter.}
\startcombination[2*1]
{\boxedgraphic{CaseInv}}{The architecture described by the Haskell description.}
\stopcombination
+ \placeexample[][ex:CaseInvVHDL]{\VHDL\ generated for \hs{inv} from
+ \in{example}[ex:CaseInv] and \in{example}[ex:PatternInv]}
+ {\typebuffervhdl{CaseInvVHDL}}
+
\startbuffer[PatternInv]
inv :: Bool -> Bool
inv True = False