Merge branch 'master' of git://github.com/christiaanb/clash into cλash

* 'master' of git://github.com/christiaanb/clash:
  Use boolean as write enable signal

diff --combined cλash/CLasH/VHDL/Generate.hs
index 9e2d0a5f6b231015d2b3b70c674b485f2f5b2445,ecaad6250c139681f83f23f3a486c461edcf949c..048a711a1e58e6f6d455651d742b84dfad6fb720
--- 1/cλash/CLasH/VHDL/Generate.hs
--- 2/cλash/CLasH/VHDL/Generate.hs
+++ b/cλash/CLasH/VHDL/Generate.hs
@@@ -207,7 -207,7 +207,7 @@@ mkConcSm (bndr, app@(CoreSyn.App _ _))
    let valargs = get_val_args (Var.varType f) args
    genApplication (Left bndr) f (map Left valargs)
  
 --- A single alt case must be a selector. This means thee scrutinee is a simple
 +-- A single alt case must be a selector. This means the scrutinee is a simple
  -- variable, the alternative is a dataalt with a single non-wild binder that
  -- is also returned.
  mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt])) 
@@@ -881,7 -881,7 +881,7 @@@ genBlockRAM' (Left res) f args@[data_in
          wform       = AST.Wform [AST.WformElem data_in Nothing]
          ramassign      = AST.SigAssign ramloc wform
          rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
-         statement   = AST.IfSm (AST.And rising_edge_clk (wrenable AST.:=: AST.PrimLit "'1'")) [ramassign] [] Nothing
+         statement   = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
  
  -----------------------------------------------------------------------------
  -- Function to generate VHDL for applications