+ \startbuffer[And3VHDL]
+ entity and3Component_0 is
+ port (\azMyG2\ : in std_logic;
+ \bzMyI2\ : in std_logic;
+ \czMyK2\ : in std_logic;
+ \foozMySzMyS2\ : out std_logic;
+ clock : in std_logic;
+ resetn : in std_logic);
+ end entity and3Component_0;
+
+
+ architecture structural of and3Component_0 is
+ signal \argzMyMzMyM2\ : std_logic;
+ begin
+ \argzMyMzMyM2\ <= \azMyG2\ and \bzMyI2\;
+
+ \foozMySzMyS2\ <= \argzMyMzMyM2\ and \czMyK2\;
+ end architecture structural;
+ \stopbuffer
+