\frame{
\frametitle{More than just toys}
\pause
+\begin{columns}[l]
+\column{0.5\textwidth}
+\begin{figure}
+\includegraphics<2->[width=5.5cm]{reducer}
+\end{figure}
+\column{0.5\textwidth}
\begin{itemize}
- \item We designed a reduction circuit in \clash{}\pause
- \item Simulation results in Haskell match VHDL simulation results\pause
+ \item We implemented a reduction circuit in \clash{}\pause
+ \item Simulated in Haskell. VHDL simulation results match\pause
\item Synthesis completes without errors or warnings\pause
- \item For the same Virtex-4 FPGA: \pause
- \begin{itemize}
- \item Hand coded VHDL design runs at 200 MHz\pause
- \item \clash{} design runs at around 85* MHz
- \end{itemize}
+ \item Around half speed of handcoded and optimized VHDL
\end{itemize}
-\vspace{6em}
-\uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}}
+\end{columns}
}\note[itemize]{
\item Toys like the poly cpu one are good to give a quick demo
\item But we used \clash{} to design 'real' hardware
-\item Reduction circuit sums the numbers in a row of a (sparse) matrix
-\item Nice speed considering we don't optimize for it
+\item Reduction circuit sums the numbers in a row, of different length
+\item It uses a pipelined adder: multiple rows in pipeline, rows longer than pipeline
+\item We hope you see this is not a trivial problem
+\item Nice speed considering we don't optimize for it (only single example!)
}
-\begin{frame}[plain]
- \begin{centering}
- \includegraphics[height=\paperheight]{reducerschematic.png}
- \end{centering}
-\end{frame}
\ No newline at end of file
+% \begin{frame}[plain]
+% \begin{centering}
+% \includegraphics[height=\paperheight]{reducerschematic.png}
+% \end{centering}
+% \end{frame}