Fixed VHDL Type generation, vhdlTy now uses HType's to generate VHDL Types. Logic...

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL.hs

diff --git a/cλash/CLasH/VHDL.hs b/cλash/CLasH/VHDL.hs
index 8429a5786810ae52b6b72146722fcd1d44b72462..762a0f43f4facc8e142d45537c55beb21df96fb7 100644 (file)
--- a/cλash/CLasH/VHDL.hs
+++ b/cλash/CLasH/VHDL.hs
@@ -84,7 +84,8 @@ createTypesPackage ::
 createTypesPackage = do
   tyfuns <- getA (tsType .> tsTypeFuns)
   let tyfun_decls = mkBuiltInShow ++ (map snd $ Map.elems tyfuns)
-  ty_decls <- getA (tsType .> tsTypeDecls)
+  ty_decls_maybes <- getA (tsType .> tsTypeDecls)
+  let ty_decls = Maybe.catMaybes ty_decls_maybes
   let subProgSpecs = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec) tyfun_decls
   let type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ ty_decls ++ subProgSpecs)
   let type_package_body = AST.LUPackageBody $ AST.PackageBody typesId tyfun_decls