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Change \VHDL command, and use the \VHDL command more consistantly in the text
[matthijs/master-project/dsd-paper.git]
/
Makefile
1
all:
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latexmk -pdf -pv cλash.tex
3
4
clean:
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latexmk -CA
projects / matthijs / master-project / dsd-paper.git / blob