4 import qualified Control.Monad as Monad
5 import qualified Data.Map as Map
11 import qualified ForSyDe.Backend.VHDL.AST as AST
25 -- | A function to wrap a builder-like function that expects its arguments to
28 (dst -> func -> [AST.Expr] -> res)
29 -> (dst -> func -> [CoreSyn.CoreExpr] -> res)
30 genExprArgs wrap dst func args = wrap dst func args'
31 where args' = map (varToVHDLExpr.exprToVar) args
33 -- | A function to wrap a builder-like function that expects its arguments to
36 (dst -> func -> [Var.Var] -> res)
37 -> (dst -> func -> [CoreSyn.CoreExpr] -> res)
38 genVarArgs wrap dst func args = wrap dst func args'
39 where args' = map exprToVar args
41 -- | A function to wrap a builder-like function that produces an expression
42 -- and expects it to be assigned to the destination.
44 (CoreSyn.CoreBndr -> func -> [arg] -> VHDLSession AST.Expr)
45 -> (CoreSyn.CoreBndr -> func -> [arg] -> VHDLSession [AST.ConcSm])
46 genExprRes wrap dst func args = do
47 expr <- wrap dst func args
48 return $ [mkUncondAssign (Left dst) expr]
50 -- | Generate a binary operator application. The first argument should be a
51 -- constructor from the AST.Expr type, e.g. AST.And.
52 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
53 genOperator2 op = genExprArgs $ genExprRes (genOperator2' op)
54 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
55 genOperator2' op res f [arg1, arg2] = return $ op arg1 arg2
57 -- | Generate a unary operator application
58 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
59 genOperator1 op = genExprArgs $ genExprRes (genOperator1' op)
60 genOperator1' :: (AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
61 genOperator1' op res f [arg] = return $ op arg
63 -- | Generate a function call from the destination binder, function name and a
64 -- list of expressions (its arguments)
65 genFCall :: BuiltinBuilder
66 genFCall = genExprArgs $ genExprRes genFCall'
67 genFCall' :: CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
68 genFCall' res f args = do
69 let fname = varToString f
70 let el_ty = (tfvec_elem . Var.varType) res
71 id <- vectorFunId el_ty fname
72 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
73 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
75 -- | Generate a generate statement for the builtin function "map"
76 genMap :: BuiltinBuilder
77 genMap = genVarArgs genMap'
78 genMap' res f [mapped_f, arg] = do
79 signatures <- getA vsSignatures
80 let entity = Maybe.fromMaybe
81 (error $ "Using function '" ++ (varToString mapped_f) ++ "' without signature? This should not happen!")
82 (Map.lookup mapped_f signatures)
84 -- Setup the generate scheme
85 len = (tfvec_len . Var.varType) res
86 label = mkVHDLExtId ("mapVector" ++ (varToString res))
87 nPar = AST.unsafeVHDLBasicId "n"
88 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
89 genScheme = AST.ForGn nPar range
90 -- Get the entity name and port names
91 entity_id = ent_id entity
92 argports = map (Monad.liftM fst) (ent_args entity)
93 resport = (Monad.liftM fst) (ent_res entity)
95 inport = mkAssocElemIndexed (argports!!0) (varToString arg) nPar
96 outport = mkAssocElemIndexed resport (varToString res) nPar
97 clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
98 portassigns = Maybe.catMaybes [inport,outport,clk_port]
99 -- Generate the portmap
100 mapLabel = "map" ++ (AST.fromVHDLId entity_id)
101 compins = mkComponentInst mapLabel entity_id portassigns
102 -- Return the generate functions
103 genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
107 genZipWith :: BuiltinBuilder
108 genZipWith = genVarArgs genZipWith'
109 genZipWith' res f args@[zipped_f, arg1, arg2] = do
110 signatures <- getA vsSignatures
111 let entity = Maybe.fromMaybe
112 (error $ "Using function '" ++ (varToString zipped_f) ++ "' without signature? This should not happen!")
113 (Map.lookup zipped_f signatures)
115 -- Setup the generate scheme
116 len = (tfvec_len . Var.varType) res
117 label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
118 nPar = AST.unsafeVHDLBasicId "n"
119 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
120 genScheme = AST.ForGn nPar range
121 -- Get the entity name and port names
122 entity_id = ent_id entity
123 argports = map (Monad.liftM fst) (ent_args entity)
124 resport = (Monad.liftM fst) (ent_res entity)
126 inport1 = mkAssocElemIndexed (argports!!0) (varToString arg1) nPar
127 inport2 = mkAssocElemIndexed (argports!!1) (varToString arg2) nPar
128 outport = mkAssocElemIndexed resport (varToString res) nPar
129 clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
130 portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
131 -- Generate the portmap
132 mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id)
133 compins = mkComponentInst mapLabel entity_id portassigns
134 -- Return the generate functions
135 genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
139 genFoldl :: BuiltinBuilder
140 genFoldl = genVarArgs genFoldl'
141 genFoldl' resVal f [folded_f, startVal, inVec] = do
142 signatures <- getA vsSignatures
143 let entity = Maybe.fromMaybe
144 (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!")
145 (Map.lookup folded_f signatures)
146 let (vec, _) = splitAppTy (Var.varType inVec)
147 let vecty = Type.mkAppTy vec (Var.varType startVal)
148 vecType <- vhdl_ty vecty
149 -- Setup the generate scheme
150 let len = (tfvec_len . Var.varType) inVec
151 let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
152 let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
153 let nPar = AST.unsafeVHDLBasicId "n"
154 let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
155 let genScheme = AST.ForGn nPar range
156 -- Make the intermediate vector
157 let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing
158 -- Return the generate functions
159 let genSm = AST.GenerateSm genlabel genScheme [] [ AST.CSGSm (genFirstCell entity [startVal, inVec, resVal])
160 , AST.CSGSm (genOtherCell entity [startVal, inVec, resVal])
161 , AST.CSGSm (genLastCell entity [startVal, inVec, resVal])
163 return [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]]
165 genFirstCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm
166 genFirstCell entity [startVal, inVec, resVal] = cellGn
168 cellLabel = mkVHDLExtId "firstcell"
169 cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0"))
170 nPar = AST.unsafeVHDLBasicId "n"
171 -- Get the entity name and port names
172 entity_id = ent_id entity
173 argports = map (Monad.liftM fst) (ent_args entity)
174 resport = (Monad.liftM fst) (ent_res entity)
176 inport1 = mkAssocElem (argports!!0) (varToString startVal)
177 inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar
178 outport = mkAssocElemIndexed resport "tmp" nPar
179 clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
180 portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
181 -- Generate the portmap
182 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
183 compins = mkComponentInst mapLabel entity_id portassigns
184 -- Return the generate functions
185 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
186 genOtherCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm
187 genOtherCell entity [startVal, inVec, resVal] = cellGn
189 len = (tfvec_len . Var.varType) inVec
190 cellLabel = mkVHDLExtId "othercell"
191 cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0"))
192 ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1)))
193 nPar = AST.unsafeVHDLBasicId "n"
194 -- Get the entity name and port names
195 entity_id = ent_id entity
196 argports = map (Monad.liftM fst) (ent_args entity)
197 resport = (Monad.liftM fst) (ent_res entity)
199 inport1 = mkAssocElemIndexed (argports!!0) "tmp" (AST.unsafeVHDLBasicId "n-1")
200 inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar
201 outport = mkAssocElemIndexed resport "tmp" nPar
202 clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
203 portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
204 -- Generate the portmap
205 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
206 compins = mkComponentInst mapLabel entity_id portassigns
207 -- Return the generate functions
208 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
209 genLastCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm
210 genLastCell entity [startVal, inVec, resVal] = cellGn
212 len = (tfvec_len . Var.varType) inVec
213 cellLabel = mkVHDLExtId "lastCell"
214 cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1)))
215 nPar = AST.unsafeVHDLBasicId "n"
216 -- Get the entity name and port names
217 entity_id = ent_id entity
218 argports = map (Monad.liftM fst) (ent_args entity)
219 resport = (Monad.liftM fst) (ent_res entity)
221 inport1 = mkAssocElemIndexed (argports!!0) "tmp" (AST.unsafeVHDLBasicId "n-1")
222 inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar
223 outport = mkAssocElemIndexed resport "tmp" nPar
224 clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
225 portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
226 -- Generate the portmap
227 mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
228 compins = mkComponentInst mapLabel entity_id portassigns
229 -- Generate the output assignment
230 assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName
231 (AST.NSimple (mkVHDLExtId "tmp")) [AST.PrimLit $ show (len-1)])))
232 -- Return the generate functions
233 cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign]
236 -- Returns the VHDLId of the vector function with the given name for the given
237 -- element type. Generates -- this function if needed.
238 vectorFunId :: Type.Type -> String -> VHDLSession AST.VHDLId
239 vectorFunId el_ty fname = do
240 elemTM <- vhdl_ty el_ty
241 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
242 -- the VHDLState or something.
243 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
244 typefuns <- getA vsTypeFuns
245 case Map.lookup (OrdType el_ty, fname) typefuns of
246 -- Function already generated, just return it
247 Just (id, _) -> return id
248 -- Function not generated yet, generate it
250 let functions = genUnconsVectorFuns elemTM vectorTM
251 case lookup fname functions of
253 modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, body)
255 Nothing -> error $ "I don't know how to generate vector function " ++ fname
257 function_id = mkVHDLExtId fname
259 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
260 -> AST.TypeMark -- ^ type of the vector
261 -> [(String, AST.SubProgBody)]
262 genUnconsVectorFuns elemTM vectorTM =
263 [ (exId, AST.SubProgBody exSpec [] [exExpr])
264 , (replaceId, AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet])
265 , (headId, AST.SubProgBody headSpec [] [headExpr])
266 , (lastId, AST.SubProgBody lastSpec [] [lastExpr])
267 , (initId, AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet])
268 , (tailId, AST.SubProgBody tailSpec [AST.SPVD tailVar] [tailExpr, tailRet])
269 , (takeId, AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet])
270 , (dropId, AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet])
271 , (plusgtId, AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet])
272 , (emptyId, AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr])
273 , (singletonId, AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet])
274 , (copyId, AST.SubProgBody copySpec [AST.SPVD copyVar] [copyExpr])
277 ixPar = AST.unsafeVHDLBasicId "ix"
278 vecPar = AST.unsafeVHDLBasicId "vec"
279 nPar = AST.unsafeVHDLBasicId "n"
280 iId = AST.unsafeVHDLBasicId "i"
282 aPar = AST.unsafeVHDLBasicId "a"
283 resId = AST.unsafeVHDLBasicId "res"
284 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
285 AST.IfaceVarDec ixPar naturalTM] elemTM
286 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
287 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
289 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
290 , AST.IfaceVarDec iPar naturalTM
291 , AST.IfaceVarDec aPar elemTM
293 -- variable res : fsvec_x (0 to vec'length-1);
296 (AST.SubtypeIn vectorTM
297 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
298 [AST.ToRange (AST.PrimLit "0")
299 (AST.PrimName (AST.NAttribute $
300 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
301 (AST.PrimLit "1")) ]))
303 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
304 replaceExpr = AST.NSimple resId AST.:=
305 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
306 AST.PrimName (AST.NSimple aPar) AST.:&:
307 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
308 ((AST.PrimName (AST.NAttribute $
309 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
310 AST.:-: AST.PrimLit "1"))
311 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
312 vecSlice init last = AST.PrimName (AST.NSlice
315 (AST.ToRange init last)))
316 headSpec = AST.Function (mkVHDLExtId headId) [AST.IfaceVarDec vecPar vectorTM] elemTM
318 headExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
319 (AST.NSimple vecPar) [AST.PrimLit "0"])))
320 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
321 -- return vec(vec'length-1);
322 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
324 [AST.PrimName (AST.NAttribute $
325 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
326 AST.:-: AST.PrimLit "1"])))
327 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
328 -- variable res : fsvec_x (0 to vec'length-2);
331 (AST.SubtypeIn vectorTM
332 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
333 [AST.ToRange (AST.PrimLit "0")
334 (AST.PrimName (AST.NAttribute $
335 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
336 (AST.PrimLit "2")) ]))
338 -- resAST.:= vec(0 to vec'length-2)
339 initExpr = AST.NSimple resId AST.:= (vecSlice
341 (AST.PrimName (AST.NAttribute $
342 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
343 AST.:-: AST.PrimLit "2"))
344 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
345 tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
346 -- variable res : fsvec_x (0 to vec'length-2);
349 (AST.SubtypeIn vectorTM
350 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
351 [AST.ToRange (AST.PrimLit "0")
352 (AST.PrimName (AST.NAttribute $
353 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
354 (AST.PrimLit "2")) ]))
356 -- res AST.:= vec(1 to vec'length-1)
357 tailExpr = AST.NSimple resId AST.:= (vecSlice
359 (AST.PrimName (AST.NAttribute $
360 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
361 AST.:-: AST.PrimLit "1"))
362 tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
363 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
364 AST.IfaceVarDec vecPar vectorTM ] vectorTM
365 -- variable res : fsvec_x (0 to n-1);
368 (AST.SubtypeIn vectorTM
369 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
370 [AST.ToRange (AST.PrimLit "0")
371 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
372 (AST.PrimLit "1")) ]))
374 -- res AST.:= vec(0 to n-1)
375 takeExpr = AST.NSimple resId AST.:=
376 (vecSlice (AST.PrimLit "1")
377 (AST.PrimName (AST.NSimple $ nPar) AST.:-: AST.PrimLit "1"))
378 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
379 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
380 AST.IfaceVarDec vecPar vectorTM ] vectorTM
381 -- variable res : fsvec_x (0 to vec'length-n-1);
384 (AST.SubtypeIn vectorTM
385 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
386 [AST.ToRange (AST.PrimLit "0")
387 (AST.PrimName (AST.NAttribute $
388 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
389 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
391 -- res AST.:= vec(n to vec'length-1)
392 dropExpr = AST.NSimple resId AST.:= (vecSlice
393 (AST.PrimName $ AST.NSimple nPar)
394 (AST.PrimName (AST.NAttribute $
395 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
396 AST.:-: AST.PrimLit "1"))
397 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
398 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
399 AST.IfaceVarDec vecPar vectorTM] vectorTM
400 -- variable res : fsvec_x (0 to vec'length);
403 (AST.SubtypeIn vectorTM
404 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
405 [AST.ToRange (AST.PrimLit "0")
406 (AST.PrimName (AST.NAttribute $
407 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
409 plusgtExpr = AST.NSimple resId AST.:=
410 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
411 (AST.PrimName $ AST.NSimple vecPar))
412 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
413 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
416 (AST.SubtypeIn vectorTM Nothing)
417 (Just $ AST.PrimLit "\"\"")
418 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
419 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
421 -- variable res : fsvec_x (0 to 0) := (others => a);
424 (AST.SubtypeIn vectorTM
425 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
426 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
427 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
428 (AST.PrimName $ AST.NSimple aPar)])
429 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
430 copySpec = AST.Function (mkVHDLExtId copyId) [AST.IfaceVarDec nPar naturalTM,
431 AST.IfaceVarDec aPar elemTM ] vectorTM
432 -- variable res : fsvec_x (0 to n-1) := (others => a);
435 (AST.SubtypeIn vectorTM
436 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
437 [AST.ToRange (AST.PrimLit "0")
438 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
439 (AST.PrimLit "1")) ]))
440 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
441 (AST.PrimName $ AST.NSimple aPar)])
443 copyExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)